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mpc85xx: pcie: Implement workaround for Erratum A007815

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The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers.  This should be done
immediately after resetting the PCI Express controller.

Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Tony O'Brien
2016-12-02 09:22:34 +13:00
committed by York Sun
parent 06ad970b53
commit 09bfd962bd
4 changed files with 19 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@@ -831,6 +831,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
@@ -893,6 +894,7 @@ config ARCH_T4240
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
@@ -1081,6 +1083,9 @@ config SYS_FSL_ERRATUM_A007186
config SYS_FSL_ERRATUM_A007212
bool
config SYS_FSL_ERRATUM_A007815
bool
config SYS_FSL_ERRATUM_A007798
bool

4
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@@ -333,6 +333,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
puts("Work-around for Erratum A007907 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
puts("Work-around for Erratum A007815 enabled\n");
#endif
return 0;
}

4
arch/powerpc/include/asm/fsl_pci.h
View File

@@ -79,7 +79,9 @@ typedef struct ccsr_pci {
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
char res4[3016]; /* (- #xbf8 #x30)3016 */
char res3[2188]; /* (0x8bc - 0x30 = 2188) */
u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */
char res4[824]; /* (0xbf8 - 0x8c0 = 824) */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */