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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2017-09-05 07:11:46 -04:00
commit 08d0c53d6b
8 changed files with 155 additions and 4 deletions
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12
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
View File

@ -220,4 +220,16 @@ enum {
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
/* CRU_GLB_RST_ST */
enum {
GLB_POR_RST,
FST_GLB_RST_ST = BIT(0),
SND_GLB_RST_ST = BIT(1),
FST_GLB_TSADC_RST_ST = BIT(2),
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
GLB_RST_ST_MASK = GENMASK(5, 0),
};
#endif

39
arch/arm/mach-rockchip/rk3288-board.c
View File

@ -11,6 +11,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3288.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/qos_rk3288.h>
@ -70,10 +71,48 @@ int rk3288_qos_init(void)
return 0;
}
static void rk3288_detect_reset_reason(void)
{
struct rk3288_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
return;
switch (cru->cru_glb_rst_st) {
case GLB_POR_RST:
reason = "POR";
break;
case FST_GLB_RST_ST:
case SND_GLB_RST_ST:
reason = "RST";
break;
case FST_GLB_TSADC_RST_ST:
case SND_GLB_TSADC_RST_ST:
reason = "THERMAL";
break;
case FST_GLB_WDT_RST_ST:
case SND_GLB_WDT_RST_ST:
reason = "WDOG";
break;
default:
reason = "unknown reset";
}
env_set("reset_reason", reason);
/*
* Clear cru_glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
}
int board_late_init(void)
{
setup_boot_mode();
rk3288_qos_init();
rk3288_detect_reset_reason();
return rk_board_late_init();
}

62
board/phytec/phycore_rk3288/phycore-rk3288.c
View File

@ -5,4 +5,66 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <i2c_eeprom.h>
#include <netdev.h>
#include "som.h"
static int valid_rk3288_som(struct rk3288_som *som)
{
unsigned char *p = (unsigned char *)som;
unsigned char *e = p + sizeof(struct rk3288_som) - 1;
int hw = 0;
while (p < e) {
hw += hweight8(*p);
p++;
}
return hw == som->bs;
}
int rk_board_late_init(void)
{
int ret;
struct udevice *dev;
struct rk3288_som opt;
int off;
/* Get the identificatioin page of M24C32-D EEPROM */
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
return off;
}
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
printf("%s: Could not find EEPROM\n", __func__);
return ret;
}
ret = i2c_set_chip_offset_len(dev, 2);
if (ret)
return ret;
ret = i2c_eeprom_read(dev, 0, (uint8_t *)&opt,
sizeof(struct rk3288_som));
if (ret) {
printf("%s: Could not read EEPROM\n", __func__);
return ret;
}
if (opt.api_version != 0 || !valid_rk3288_som(&opt)) {
printf("Invalid data or wrong EEPROM layout version.\n");
/* Proceed anyway, since there is no fallback option */
}
if (is_valid_ethaddr(opt.mac))
eth_env_set_enetaddr("ethaddr", opt.mac);
return 0;
}

21
board/phytec/phycore_rk3288/som.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright (C) 2017 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* rk3288_som struct represents the eeprom layout for PHYTEC RK3288 based SoMs
*/
struct rk3288_som {
unsigned char api_version; /* EEPROM layout API version */
unsigned char mod_version; /* PCM/PFL/PCA */
unsigned char option[12]; /* coding for variants */
unsigned char som_rev; /* SOM revision */
unsigned char mac[6];
unsigned char ksp; /* 1: KSP, 2: KSM */
unsigned char kspno; /* Number for KSP/KSM module */
unsigned char reserved[8]; /* not used */
unsigned char bs; /* Bits set in previous bytes */
} __attribute__ ((__packed__));

2
configs/firefly-rk3399_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_ATF_SUPPORT=y
CONFIG_SPL_ATF_TEXT_BASE=0x00010000
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPT=y

2
configs/phycore-rk3288_defconfig
View File

@ -46,6 +46,8 @@ CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_DM_ETH=y

19
drivers/i2c/rk_i2c.c
View File

@ -164,6 +164,7 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
uint rxdata;
uint i, j;
int err;
bool snd_chunk = false;
debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
chip, reg, r_len, b_len);
@ -184,15 +185,26 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
while (bytes_remain_len) {
if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
con = I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TRX);
con = I2C_CON_EN;
bytes_xferred = 32;
} else {
con = I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TRX) |
I2C_CON_LASTACK;
/*
* The hw can read up to 32 bytes at a time. If we need
* more than one chunk, send an ACK after the last byte.
*/
con = I2C_CON_EN | I2C_CON_LASTACK;
bytes_xferred = bytes_remain_len;
}
words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
/*
* make sure we are in plain RX mode if we read a second chunk
*/
if (snd_chunk)
con |= I2C_CON_MOD(I2C_MODE_RX);
else
con |= I2C_CON_MOD(I2C_MODE_TRX);
writel(con, &regs->con);
writel(bytes_xferred, &regs->mrxcnt);
writel(I2C_MBRFIEN | I2C_NAKRCVIEN, &regs->ien);
@ -227,6 +239,7 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
}
bytes_remain_len -= bytes_xferred;
snd_chunk = true;
debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
}

2
drivers/timer/rockchip_timer.c
View File

@ -92,7 +92,7 @@ static const struct udevice_id rockchip_timer_ids[] = {
{}
};
U_BOOT_DRIVER(arc_timer) = {
U_BOOT_DRIVER(rockchip_rk3368_timer) = {
.name = "rockchip_rk3368_timer",
.id = UCLASS_TIMER,
.of_match = rockchip_timer_ids,