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imx: iomux: fix snvs usage for i.MX6ULL

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SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.

Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Peng Fan 2016-08-11 14:02:51 +08:00 committed by Stefano Babic
parent 5b66482d44
commit 07e1c0ae83
3 changed files with 14 additions and 4 deletions
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11
arch/arm/imx-common/iomux-v3.c
View File

@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#ifdef CONFIG_IOMUX_LPSR
u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
#ifdef CONFIG_MX7
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_LPSR_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (sel_input_ofs)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
#else
if (is_mx6ull()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
}
}
#endif
#endif
if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)

1
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -182,6 +182,7 @@
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)

6
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@ -85,12 +85,12 @@ typedef u64 iomux_v3_cfg_t;
#define NO_PAD_CTRL (1 << 17)
#ifdef CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
#define IOMUX_CONFIG_LPSR 0x8
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_MX7
#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0)
#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0)