i2c: ihs_i2c: Dual channel support
Support two i2c masters per FPGA. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Acked-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Dirk Eibach
Tom Rini
parent
5b47d407e4
commit
071be89694
9
README
9
README
@ -2438,6 +2438,15 @@ CBFS (Coreboot Filesystem) support
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- CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
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- CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
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- CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
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- activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
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- CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
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- CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
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- CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
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- CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
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- CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
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- CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
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- CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
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- CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
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additional defines:
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@ -11,6 +11,28 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_SET_REG(fld, val) \
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{ if (I2C_ADAP_HWNR & 0x10) \
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FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
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#else
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#define I2C_SET_REG(fld, val) \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_GET_REG(fld, val) \
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{ if (I2C_ADAP_HWNR & 0x10) \
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FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
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#else
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#define I2C_GET_REG(fld, val) \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
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#endif
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enum {
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I2CINT_ERROR_EV = 1 << 13,
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I2CINT_TRANSMIT_EV = 1 << 14,
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@ -29,14 +51,14 @@ static int wait_for_int(bool read)
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u16 val;
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unsigned int ctr = 0;
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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I2C_GET_REG(interrupt_status, &val);
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while (!(val & (I2CINT_ERROR_EV
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| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
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udelay(10);
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if (ctr++ > 5000) {
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return 1;
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}
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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I2C_GET_REG(interrupt_status, &val);
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}
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return (val & I2CINT_ERROR_EV) ? 1 : 0;
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@ -47,19 +69,19 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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{
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u16 val;
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
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I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV
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| I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
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I2C_GET_REG(interrupt_status, &val);
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if (!read && len) {
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val = buffer[0];
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if (len > 1)
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val |= buffer[1] << 8;
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
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I2C_SET_REG(write_mailbox_ext, val);
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}
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
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I2C_SET_REG(write_mailbox,
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I2CMB_NATIVE
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| (read ? 0 : I2CMB_WRITE)
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| (chip << 1)
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@ -70,7 +92,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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return 1;
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if (read) {
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
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I2C_GET_REG(read_mailbox_ext, &val);
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buffer[0] = val & 0xff;
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if (len > 1)
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buffer[1] = val >> 8;
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@ -179,6 +201,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0,
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CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0_1,
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CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH1
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U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
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@ -186,6 +215,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH2
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U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
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@ -193,6 +229,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2,
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CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2_1,
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CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH3
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U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
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@ -200,4 +243,11 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3,
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CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3_1,
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CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
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#endif
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#endif
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@ -143,7 +143,7 @@ struct ihs_fpga {
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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struct ihs_i2c i2c; /* 0x0040 */
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struct ihs_i2c i2c0; /* 0x0040 */
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u16 reserved_4[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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@ -177,7 +177,7 @@ struct ihs_fpga {
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u16 reserved_2[2]; /* 0x001c */
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struct ihs_io_ep ep; /* 0x0020 */
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u16 reserved_3[9]; /* 0x002e */
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struct ihs_i2c i2c; /* 0x0040 */
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struct ihs_i2c i2c0; /* 0x0040 */
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u16 reserved_4[10]; /* 0x004c */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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@ -208,10 +208,12 @@ struct ihs_fpga {
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u16 reserved_1[29]; /* 0x001e */
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u16 mpc3w_control; /* 0x0058 */
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u16 reserved_2[3]; /* 0x005a */
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struct ihs_i2c i2c; /* 0x0060 */
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u16 reserved_3[205]; /* 0x0066 */
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struct ihs_i2c i2c0; /* 0x0060 */
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u16 reserved_3[2]; /* 0x006c */
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struct ihs_i2c i2c1; /* 0x0070 */
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u16 reserved_4[194]; /* 0x007c */
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struct ihs_osd osd; /* 0x0200 */
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u16 reserved_4[761]; /* 0x020e */
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u16 reserved_5[761]; /* 0x020e */
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u16 videomem[31736]; /* 0x0800 */
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};
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#endif
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