powerpc/mpc83xx: add support for new SPL
This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Scott Wood
Kim Phillips
parent
74752baa73
commit
06f60ae3e4
6
README
6
README
@ -2779,6 +2779,12 @@ FIT uImage format:
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CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
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Filename to read to load U-Boot when reading from FAT
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CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
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Set this for NAND SPL on PPC mpc83xx targets, so that
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start.S waits for the rest of the SPL to load before
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continuing (the hardware starts execution after just
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loading the first page rather than the full 4K).
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CONFIG_SPL_NAND_BASE
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Include nand_base.c in the SPL. Requires
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CONFIG_SPL_NAND_DRIVERS.
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@ -27,8 +27,22 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).o
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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START = start.o
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ifdef MINIMAL
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COBJS-y += spl_minimal.o
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else
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COBJS-y += traps.o
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COBJS-y += cpu.o
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COBJS-y += cpu_init.o
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@ -51,6 +65,8 @@ COBJS-y += spd_sdram.o
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endif
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COBJS-$(CONFIG_FSL_DDR2) += law.o
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endif # not minimal
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COBJS := $(COBJS-y)
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
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@ -58,7 +58,13 @@
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#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
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#endif
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#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_NAND_SPL) || \
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(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
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#define MINIMAL_SPL
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#endif
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#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
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!defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_SYS_FLASHBOOT
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#endif
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@ -72,7 +78,7 @@
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GOT_ENTRY(__bss_start)
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GOT_ENTRY(__bss_end__)
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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@ -206,7 +212,8 @@ _start: /* time t 0 */
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/* Initialise the E300 processor core */
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/*------------------------------------------*/
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#ifdef CONFIG_NAND_SPL
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#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
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defined(CONFIG_NAND_SPL)
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/* The FCM begins execution after only the first page
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* is loaded. Wait for the rest before branching
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* to another flash page.
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@ -292,7 +299,7 @@ in_flash:
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/* NOTREACHED - board_init_f() does not return */
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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/*
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* Vector Table
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*/
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@ -467,7 +474,7 @@ int_return:
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lwz r1,GPR1(r1)
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SYNC
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rfi
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#endif /* !CONFIG_NAND_SPL */
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#endif /* !MINIMAL_SPL */
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/*
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* This code initialises the E300 processor core
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@ -724,7 +731,7 @@ setup_bats:
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* Note: requires that all cache bits in
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* HID0 are in the low half word.
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*/
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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.globl icache_enable
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icache_enable:
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mfspr r3, HID0
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@ -753,7 +760,7 @@ icache_status:
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mfspr r3, HID0
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rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
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blr
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#endif /* !CONFIG_NAND_SPL */
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#endif /* !MINIMAL_SPL */
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.globl dcache_enable
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dcache_enable:
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@ -936,7 +943,7 @@ in_ram:
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stw r0,0(r3)
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2: bdnz 1b
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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/*
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* Now adjust the fixups and the pointers to the fixups
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* in case we need to move ourselves again.
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@ -991,7 +998,7 @@ clear_bss:
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mr r4, r10 /* Destination Address */
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bl board_init_r
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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/*
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* Copy exception vector code to low memory
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*
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@ -1061,7 +1068,7 @@ trap_init:
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mtlr r4 /* restore link register */
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blr
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#endif /* !CONFIG_NAND_SPL */
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#endif /* !MINIMAL_SPL */
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#ifdef CONFIG_SYS_INIT_RAM_LOCK
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lock_ram_in_cache:
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@ -1085,7 +1092,7 @@ lock_ram_in_cache:
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sync
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blr
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#ifndef CONFIG_NAND_SPL
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#ifndef MINIMAL_SPL
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.globl unlock_ram_in_cache
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unlock_ram_in_cache:
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/* invalidate the INIT_RAM section */
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@ -1111,7 +1118,7 @@ unlock_ram_in_cache:
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sync
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mtspr HID0, r3 /* no invalidate, unlock */
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blr
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#endif /* !CONFIG_NAND_SPL */
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#endif /* !MINIMAL_SPL */
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#endif /* CONFIG_SYS_INIT_RAM_LOCK */
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#ifdef CONFIG_SYS_FLASHBOOT
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55
arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
Normal file
55
arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
Normal file
@ -0,0 +1,55 @@
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/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_ARCH(powerpc)
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SECTIONS
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{
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. = 0xfff00000;
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.text : {
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*(.text*)
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. = ALIGN(16);
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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}
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. = ALIGN(8);
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.data : {
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*(.data*)
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*(.sdata*)
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_GOT2_TABLE_ = .;
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KEEP(*(.got2))
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KEEP(*(.got))
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
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}
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
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. = ALIGN(8);
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__bss_start = .;
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.bss (NOLOAD) : {
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*(.*bss)
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}
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__bss_end__ = .;
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}
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ENTRY(_start)
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ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big");
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@ -47,7 +47,8 @@ endif
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endif
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ifdef MINIMAL
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COBJS-y += cache.o
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COBJS-y += cache.o time.o
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SOBJS-y += ticks.o
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else
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SOBJS-y += ppcstring.o
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@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o ticks.o
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
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time.o cache.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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@ -80,8 +80,8 @@ $(obj)$(BOARD).c:
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$(obj)ns16550.c:
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)nand_init.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
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$(obj)spl_minimal.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
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$(obj)cache.c:
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ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
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@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o ticks.o
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
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time.o cache.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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@ -80,8 +80,8 @@ $(obj)$(BOARD).c:
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$(obj)ns16550.c:
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)nand_init.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
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$(obj)spl_minimal.c:
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ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
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$(obj)cache.c:
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ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
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@ -36,7 +36,7 @@ AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o ticks.o
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
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COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
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time.o cache.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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@ -84,9 +84,9 @@ $(obj)ns16550.c:
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@rm -f $@
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ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
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$(obj)nand_init.c:
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$(obj)spl_minimal.c:
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
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$(obj)cache.c:
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@rm -f $@
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