Merge git://git.denx.de/u-boot-fsl-qoriq

2017-01-19 12:22:23 -05:00
parent 755b06d1c0 5e4a6db8f4
commit 0675f992db
123 changed files with 2844 additions and 979 deletions
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -28,8 +28,9 @@
 #define CONFIG_FSL_TZASC_400
 #endif

-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */

 /* DDR */
 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
@@ -122,7 +123,11 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
+
+#define DCSR_DCFG_SBEESR2			0x20140534
+#define DCSR_DCFG_MBEESR2			0x20140544

 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
@@ -158,6 +163,28 @@
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
+#define GICH_BASE		0x01404000
+#define GICV_BASE		0x01406000
+#define GICD_SIZE		0x1000
+#define GICC_SIZE		0x2000
+#define GICH_SIZE		0x2000
+#define GICV_SIZE		0x2000
+#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
+#define GICD_BASE_64K		0x01410000
+#define GICC_BASE_64K		0x01420000
+#define GICH_BASE_64K		0x01440000
+#define GICV_BASE_64K		0x01460000
+#define GICD_SIZE_64K		0x10000
+#define GICC_SIZE_64K		0x20000
+#define GICH_SIZE_64K		0x20000
+#define GICV_SIZE_64K		0x20000
+#endif
+
+#define DCFG_CCSR_SVR		0x1ee00a4
+#define REV1_0			0x10
+#define REV1_1			0x11
+#define GIC_ADDR_BIT		31
+#define SCFG_GIC400_ALIGN	0x1570188

 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1

--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -93,7 +93,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
@@ -140,7 +140,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
@@ -178,7 +178,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@@ -280,7 +280,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-	  CONFIG_SYS_FSL_OCRAM_SIZE,
+	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
--- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -7,9 +7,5 @@
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
 #define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_

-void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
-void append_mmu_masters(void *blob, const char *smmu_path,
-			const char *master_name, u32 *stream_ids, int count);
-void fdt_fixup_smmu_pcie(void *blob);
 void fdt_fixup_board_enet(void *fdt);
 #endif	/* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -162,6 +162,14 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl);
 #ifdef CONFIG_FSL_LSCH2
 const char *serdes_clock_to_string(u32 clock);
 int get_serdes_protocol(void);
+#ifdef CONFIG_SYS_HAS_SERDES
+/* Get the volt of SVDD in unit mV */
+int get_serdes_volt(void);
+/* Set the volt of SVDD in unit mV */
+int set_serdes_volt(int svdd);
+/* The target volt of SVDD in unit mV */
+int setup_serdes_volt(u32 svdd);
+#endif
 #endif

 #endif /* __FSL_SERDES_H__ */
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -137,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."

 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 	unsigned long freq_localbus;
@@ -360,7 +361,8 @@ struct ccsr_scfg {
 	u32 qspi_cfg;
 	u8 res_160[0x180-0x160];
 	u32 dmamcr;
-	u8 res_184[0x18c-0x184];
+	u8 res_184[0x188-0x184];
+	u32 gic_align;
 	u32 debug_icid;
 	u8 res_190[0x1a4-0x190];
 	u32 snpcnfgcr;
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -107,14 +107,6 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
-/* LUT registers */
-#define PCIE_LUT_BASE				0x80000
-#define PCIE_LUT_LCTRL0				0x7F8
-#define PCIE_LUT_DBG				0x7FC
-#define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
-#define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
-#define PCIE_LUT_ENABLE         (1 << 31)
-#define PCIE_LUT_ENTRY_COUNT    32

 /* Device Configuration */
 #define DCFG_BASE		0x01e00000
@@ -159,6 +151,7 @@
 #ifndef __ASSEMBLY__
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -59,6 +59,7 @@ struct cpu_type {

 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
+#define SVR_REV(svr)		(((svr) >> 0) & 0xff)
 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
@@ -99,6 +100,9 @@ struct ccsr_ahci {
 void fsl_lsch3_early_init_f(void);
 #elif defined(CONFIG_FSL_LSCH2)
 void fsl_lsch2_early_init_f(void);
+int setup_chip_volt(void);
+/* Setup core vdd in unit mV */
+int board_setup_core_volt(u32 vdd);
 #endif

 void cpu_name(char *name);
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
+#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
 unsigned int sec_firmware_support_psci_version(void);
 unsigned int _sec_firmware_support_psci_version(void);
 #endif
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -80,18 +80,18 @@

 /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
 * Non-XIP Memory (Nand/SD)*/
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
 	defined(CONFIG_SD_BOOT)
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif
 /* The address needs to be modified according to NOR, NAND, SD and
 * DDR memory map
 */
-#ifdef CONFIG_LS2080A
-#define CONFIG_BS_HDR_ADDR_DEVICE	0x583920000
-#define CONFIG_BS_ADDR_DEVICE		0x583900000
-#define CONFIG_BS_HDR_ADDR_RAM		0xa3920000
-#define CONFIG_BS_ADDR_RAM		0xa3900000
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x580d00000
+#define CONFIG_BS_ADDR_DEVICE		0x580e00000
+#define CONFIG_BS_HDR_ADDR_RAM		0xa0d00000
+#define CONFIG_BS_ADDR_RAM		0xa0e00000
 #define CONFIG_BS_HDR_SIZE		0x00002000
 #define CONFIG_BS_SIZE			0x00001000
 #else
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -196,11 +196,12 @@ void __asm_switch_ttbr(u64 new_ttbr);
 *               For loading 32-bit OS, machine nr
 * @fdt_addr:    For loading 64-bit OS, zero.
 *               For loading 32-bit OS, fdt address.
+ * @arg4:	 Input argument.
 * @entry_point: kernel entry point
 * @es_flag:     execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
 */
 void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
-			 u64 entry_point, u64 es_flag);
+			 u64 arg4, u64 entry_point, u64 es_flag);
 /*
 * Switch from EL2 to EL1 for ARMv8
 *
@@ -210,13 +211,14 @@ void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
 *               For loading 32-bit OS, machine nr
 * @fdt_addr:    For loading 64-bit OS, zero.
 *               For loading 32-bit OS, fdt address.
+ * @arg4:	 Input argument.
 * @entry_point: kernel entry point
 * @es_flag:     execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
 */
 void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
-			 u64 entry_point, u64 es_flag);
+			 u64 arg4, u64 entry_point, u64 es_flag);
 void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
-			  u64 entry_point);
+			  u64 arg4, u64 entry_point);
 void gic_init(void);
 void gic_send_sgi(unsigned long sgino);
 void wait_for_wakeup(void);