driver: watchdog: add sp805 watchdog support
sp805 is watchdog on some NXP layerscape SoCs, adding it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT needs to be enabled to use it. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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@ -519,6 +519,7 @@ FREESCALE QORIQ
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M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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S: Maintained
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T: git git://git.denx.de/u-boot-fsl-qoriq.git
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F: drivers/watchdog/sp805_wdt.c
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I2C
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M: Heiko Schocher <hs@denx.de>
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@ -103,6 +103,13 @@ config WDT_ORION
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Select this to enable Orion watchdog timer, which can be found on some
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Marvell Armada chips.
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config WDT_SP805
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bool "SP805 watchdog timer support"
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depends on WDT
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help
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Select this to enable SP805 watchdog timer, which can be found on some
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nxp layerscape chips.
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config WDT_CDNS
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bool "Cadence watchdog timer support"
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depends on WDT
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@ -27,3 +27,4 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
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obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
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obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
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obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
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obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
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127
drivers/watchdog/sp805_wdt.c
Normal file
127
drivers/watchdog/sp805_wdt.c
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@ -0,0 +1,127 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Watchdog driver for SP805 on some Layerscape SoC
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*
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* Copyright 2019 NXP
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <dm/read.h>
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#include <linux/bitops.h>
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#include <watchdog.h>
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#include <wdt.h>
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#define WDTLOAD 0x000
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#define WDTCONTROL 0x008
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#define WDTINTCLR 0x00C
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#define WDTLOCK 0xC00
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#define TIME_OUT_MIN_MSECS 1
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#define TIME_OUT_MAX_MSECS 120000
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#define SYS_FSL_WDT_CLK_DIV 16
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#define INT_ENABLE BIT(0)
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#define RESET_ENABLE BIT(1)
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#define DISABLE 0
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#define UNLOCK 0x1ACCE551
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#define LOCK 0x00000001
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#define INT_MASK BIT(0)
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DECLARE_GLOBAL_DATA_PTR;
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struct sp805_wdt_priv {
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void __iomem *reg;
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};
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static int sp805_wdt_reset(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(INT_MASK, priv->reg + WDTINTCLR);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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u32 load_value;
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u32 load_time;
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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load_time = (u32)timeout;
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if (timeout < TIME_OUT_MIN_MSECS)
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load_time = TIME_OUT_MIN_MSECS;
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else if (timeout > TIME_OUT_MAX_MSECS)
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load_time = TIME_OUT_MAX_MSECS;
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/* sp805 runs counter with given value twice, so when the max timeout is
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* set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
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* not overflow.
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*/
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load_value = (gd->bus_clk) /
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(2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(load_value, priv->reg + WDTLOAD);
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writel(INT_MASK, priv->reg + WDTINTCLR);
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writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_stop(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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writel(UNLOCK, priv->reg + WDTLOCK);
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writel(DISABLE, priv->reg + WDTCONTROL);
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writel(LOCK, priv->reg + WDTLOCK);
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readl(priv->reg + WDTLOCK);
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return 0;
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}
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static int sp805_wdt_probe(struct udevice *dev)
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{
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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return 0;
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}
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static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct sp805_wdt_priv *priv = dev_get_priv(dev);
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priv->reg = (void __iomem *)dev_read_addr(dev);
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if (IS_ERR(priv->reg))
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return PTR_ERR(priv->reg);
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return 0;
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}
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static const struct wdt_ops sp805_wdt_ops = {
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.start = sp805_wdt_start,
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.reset = sp805_wdt_reset,
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.stop = sp805_wdt_stop,
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};
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static const struct udevice_id sp805_wdt_ids[] = {
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{ .compatible = "arm,sp805-wdt" },
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{}
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};
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U_BOOT_DRIVER(sp805_wdt) = {
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.name = "sp805_wdt",
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.id = UCLASS_WDT,
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.of_match = sp805_wdt_ids,
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.probe = sp805_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
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.ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
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.ops = &sp805_wdt_ops,
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};
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