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powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x

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There was for long time no activity in the mpx5xxx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in mpc5xxx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher 2017-06-14 05:49:40 +02:00 committed by Tom Rini
parent 88024dc5ac
commit 064b55cfcb
269 changed files with 14 additions and 34007 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
.travis.yml
View File

@ -193,12 +193,6 @@ matrix:
- env:
- BUILDMAN="mips"
TOOLCHAIN="mips"
- env:
- BUILDMAN="mpc512x"
- env:
- BUILDMAN="mpc5xx"
- env:
- BUILDMAN="mpc5xxx"
- env:
- BUILDMAN="mpc83xx"
- env:

6
MAINTAINERS
View File

@ -321,12 +321,6 @@ M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: arch/powerpc/
POWERPC MPC5XXX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc5xxx.git
F: arch/powerpc/cpu/mpc5*/
POWERPC MPC8XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained

25
README
View File

@ -608,10 +608,6 @@ The following options need to be configured:
* Adds the "fdt" command
* The bootm command automatically updates the fdt
OF_CPU - The proper name of the cpus node (only required for
MPC512X and MPC5xxx based boards).
OF_SOC - The proper name of the soc node (only required for
MPC512X and MPC5xxx based boards).
OF_TBCLK - The timebase frequency.
OF_STDOUT_PATH - The path to the console device
@ -1232,7 +1228,7 @@ The following options need to be configured:
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define
supported (PIP405, MIP405); define
CONFIG_USB_UHCI to enable it.
define CONFIG_USB_KEYBOARD to enable the USB Keyboard
and define CONFIG_USB_STORAGE to enable the USB
@ -1240,19 +1236,6 @@ The following options need to be configured:
Note:
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
MPC5200 USB requires additional defines:
CONFIG_USB_CLOCK
for 528 MHz Clock: 0x0001bbbb
CONFIG_PSC3_USB
for USB on PSC3
CONFIG_USB_CONFIG
for differential drivers: 0x00001000
for single ended drivers: 0x00005000
for differential drivers on PSC3: 0x00000100
for single ended drivers on PSC3: 0x00004100
CONFIG_SYS_USB_EVENT_POLL
May be defined to allow interrupt polling
instead of using asynchronous interrupts
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
@ -1894,12 +1877,6 @@ The following options need to be configured:
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
- CAN Support: CONFIG_CAN_DRIVER
Defining CONFIG_CAN_DRIVER enables CAN driver support
on those systems that support this (optional)
feature.
- I2C Support: CONFIG_SYS_I2C
This enable the NEW i2c subsystem, and will allow you to use

2
api/api_platform-powerpc.c
View File

@ -32,8 +32,6 @@ int platform_sys_info(struct sys_info *si)
#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC5xxx)
#define bi_bar bi_mbar_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
#endif

8
arch/powerpc/Kconfig
View File

@ -8,12 +8,6 @@ choice
prompt "CPU select"
optional
config MPC512X
bool "MPC512X"
config MPC5xxx
bool "MPC5xxx"
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
@ -42,8 +36,6 @@ config 4xx
endchoice
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"

34
arch/powerpc/cpu/mpc512x/Kconfig
View File

@ -1,34 +0,0 @@
menu "mpc512x CPU"
depends on MPC512X
config SYS_CPU
default "mpc512x"
choice
prompt "Target select"
optional
config TARGET_PDM360NG
bool "Support pdm360ng"
config TARGET_ARIA
bool "Support aria"
config TARGET_MECP5123
bool "Support mecp5123"
config TARGET_MPC5121ADS
bool "Support mpc5121ads"
config TARGET_AC14XX
bool "Support ac14xx"
endchoice
source "board/davedenx/aria/Kconfig"
source "board/esd/mecp5123/Kconfig"
source "board/freescale/mpc5121ads/Kconfig"
source "board/ifm/ac14xx/Kconfig"
source "board/pdm360ng/Kconfig"
endmenu

18
arch/powerpc/cpu/mpc512x/Makefile
View File

@ -1,18 +0,0 @@
#
# (C) Copyright 2007-2009 DENX Software Engineering
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
obj-y := cpu.o
obj-y += traps.o
obj-y += cpu_init.o
obj-y += fixed_sdram.o
obj-y += interrupts.o
obj-y += iopin.o
obj-y += serial.o
obj-y += speed.o
obj-$(CONFIG_FSL_DIU_FB) += diu.o
obj-$(CONFIG_CMD_IDE) += ide.o
obj-$(CONFIG_PCI) += pci.o

15
arch/powerpc/cpu/mpc512x/asm-offsets.h
View File

@ -1,15 +0,0 @@
/*
* needed for arch/powerpc/cpu/mpc512x/start.S
*
* These should be auto-generated
*/
#define LPCS0AW 0x0024
#define SRAMBAR 0x00C4
#define SWCRR 0x0904
#define LPC_OFFSET 0x10000
#define CS0_CONFIG 0x00000
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET

7
arch/powerpc/cpu/mpc512x/config.mk
View File

@ -1,7 +0,0 @@
#
# (C) Copyright 2007-2010 DENX Software Engineering
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e

193
arch/powerpc/cpu/mpc512x/cpu.c
View File

@ -1,193 +0,0 @@
/*
* (C) Copyright 2007-2010 DENX Software Engineering
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* CPU specific code for the MPC512x family.
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/io.h>
#if defined(CONFIG_OF_LIBFDT)
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ulong clock = gd->cpu_clk;
u32 pvr = get_pvr ();
u32 spridr = in_be32(&immr->sysconf.spridr);
char buf1[32], buf2[32];
puts ("CPU: ");
switch (spridr & 0xffff0000) {
case SPR_5121E:
puts ("MPC5121e ");
break;
default:
printf ("Unknown part ID %08x ", spridr & 0xffff0000);
}
printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
switch (pvr & 0xffff0000) {
case PVR_E300C4:
puts ("e300c4 ");
break;
default:
puts ("unknown ");
}
printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
strmhz(buf1, clock),
strmhz(buf2, gd->arch.csb_clk),
gd->arch.reset_status & 0xffff);
return 0;
}
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong msr;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~( MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/*
* Enable Reset Control Reg - "RSTE" is the magic word that let us go
*/
out_be32(&immap->reset.rpr, 0x52535445);
/* Verify Reset Control Reg is enabled */
while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
;
printf ("Resetting the board.\n");
udelay(200);
/* Perform reset */
out_be32(&immap->reset.rcr, RCR_SWHR);
/* Unreached... */
return 1;
}
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*/
unsigned long get_tbclk (void)
{
return (gd->bus_clk + 3L) / 4L;
}
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
/* Reset watchdog */
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
out_be32(&immr->wdt.swsrr, 0x556c);
out_be32(&immr->wdt.swsrr, 0xaa39);
if (re_enable)
enable_interrupts ();
}
#endif
#ifdef CONFIG_OF_LIBFDT
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
/*
* fdt setup for old device trees
* fix up
* cpu clocks
* soc clocks
* ethernet addresses
*/
static void old_ft_cpu_setup(void *blob, bd_t *bd)
{
/*
* avoid fixing up by path because that
* produces scary error messages
*/
uchar enetaddr[6];
/*
* old device trees have ethernet nodes with
* device_type = "network"
*/
eth_getenv_enetaddr("ethaddr", enetaddr);
do_fixup_by_prop(blob, "device_type", "network", 8,
"local-mac-address", enetaddr, 6, 0);
do_fixup_by_prop(blob, "device_type", "network", 8,
"address", enetaddr, 6, 0);
/*
* old device trees have soc nodes with
* device_type = "soc"
*/
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_ipsfreq, 0);
}
#endif
static void ft_clock_setup(void *blob, bd_t *bd)
{
char *cpu_path = "/cpus/" OF_CPU;
/*
* fixup cpu clocks using path
*/
do_fixup_by_path_u32(blob, cpu_path,
"timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path,
"clock-frequency", bd->bi_intfreq, 1);
/*
* fixup soc clocks using compatible
*/
do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
"bus-frequency", bd->bi_ipsfreq, 1);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
old_ft_cpu_setup(blob, bd);
#endif
ft_clock_setup(blob, bd);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif
#ifdef CONFIG_MPC512x_FEC
/* Default initializations for FEC controllers. To override,
* create a board-specific function called:
* int board_eth_init(bd_t *bis)
*/
int cpu_eth_init(bd_t *bis)
{
return mpc512x_fec_initialize(bis);
}
#endif

195
arch/powerpc/cpu/mpc512x/cpu_init.c
View File

@ -1,195 +0,0 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2007-2009 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*
* Derived from the MPC83xx code.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/mpc512x.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Set up the memory map, initialize registers,
*/
void cpu_init_f (volatile immap_t * im)
{
u32 ips_div;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* Local Window and chip select configuration */
#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
out_be32(&im->sysconf.lpcs0aw,
CSAW_START(CONFIG_SYS_CS0_START) |
CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
sync_law(&im->sysconf.lpcs0aw);
#endif
#if defined(CONFIG_SYS_CS0_CFG)
out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
#endif
#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
out_be32(&im->sysconf.lpcs1aw,
CSAW_START(CONFIG_SYS_CS1_START) |
CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
sync_law(&im->sysconf.lpcs1aw);
#endif
#if defined(CONFIG_SYS_CS1_CFG)
out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
#endif
#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
out_be32(&im->sysconf.lpcs2aw,
CSAW_START(CONFIG_SYS_CS2_START) |
CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
sync_law(&im->sysconf.lpcs2aw);
#endif
#if defined(CONFIG_SYS_CS2_CFG)
out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
#endif
#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
out_be32(&im->sysconf.lpcs3aw,
CSAW_START(CONFIG_SYS_CS3_START) |
CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
sync_law(&im->sysconf.lpcs3aw);
#endif
#if defined(CONFIG_SYS_CS3_CFG)
out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
#endif
#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
out_be32(&im->sysconf.lpcs4aw,
CSAW_START(CONFIG_SYS_CS4_START) |
CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
sync_law(&im->sysconf.lpcs4aw);
#endif
#if defined(CONFIG_SYS_CS4_CFG)
out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
#endif
#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
out_be32(&im->sysconf.lpcs5aw,
CSAW_START(CONFIG_SYS_CS5_START) |
CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
sync_law(&im->sysconf.lpcs5aw);
#endif
#if defined(CONFIG_SYS_CS5_CFG)
out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
#endif
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
out_be32(&im->sysconf.lpcs6aw,
CSAW_START(CONFIG_SYS_CS6_START) |
CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
sync_law(&im->sysconf.lpcs6aw);
#endif
#if defined(CONFIG_SYS_CS6_CFG)
out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
#endif
#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
out_be32(&im->sysconf.lpcs7aw,
CSAW_START(CONFIG_SYS_CS7_START) |
CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
sync_law(&im->sysconf.lpcs7aw);
#endif
#if defined(CONFIG_SYS_CS7_CFG)
out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
#endif
#if defined CONFIG_SYS_CS_ALETIMING
if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
#endif
#if defined CONFIG_SYS_CS_BURST
out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
#endif
#if defined CONFIG_SYS_CS_DEADCYCLE
out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
#endif
#if defined CONFIG_SYS_CS_HOLDCYCLE
out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
#endif
/* system performance tweaking */
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
out_be32(&im->arbiter.acr,
(im->arbiter.acr & ~ACR_PIPE_DEP) |
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
);
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
out_be32(im->arbiter.acr,
(im->arbiter.acr & ~(ACR_RPTCNT)) |
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
);
#endif
/* RSR - Reset Status Register - clear all status */
gd->arch.reset_status = im->reset.rsr;
out_be32(&im->reset.rsr, ~RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
ips_div = in_be32(&im->clk.scfr[0]);
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
out_be32(&im->clk.scfr[0], ips_div);
#ifdef SCFR1_LPC_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
#endif
#ifdef SCFR1_NFC_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
#endif
#ifdef SCFR1_DIU_DIV
clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
#endif
/*
* Enable Time Base/Decrementer
*
* NOTICE: TB needs to be enabled as early as possible in order to
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/*
* Enable clocks
*/
out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
#endif
}
int cpu_init_r (void)
{
return 0;
}

44
arch/powerpc/cpu/mpc512x/diu.c
View File

@ -1,44 +0,0 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* York Sun <yorksun@freescale.com>
*
* FSL DIU Framebuffer driver
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <fsl_diu_fb.h>
DECLARE_GLOBAL_DATA_PTR;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile clk512x_t *clk = &immap->clk;
volatile unsigned int *clkdvdr = &clk->scfr[0];
unsigned long speed_ccb, temp, pixval;
speed_ccb = get_bus_freq(0) * 4;
temp = 1000000000/pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %lu\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
temp = in_be32(clkdvdr) & 0xFFFFFF00;
out_be32(clkdvdr, temp | (pixval & 0xFF));
debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
}
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
{
unsigned int pixel_format = 0x88883316;
debug("mpc5121_diu_init\n");
return fsl_diu_init(xres, yres, pixel_format, 0);
}

155
arch/powerpc/cpu/mpc512x/fixed_sdram.c
View File

@ -1,155 +0,0 @@
/*
* (C) Copyright 2007-2009 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/mpc512x.h>
/*
* MDDRC Config Runtime Settings
*/
ddr512x_config_t default_mddrc_config = {
.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG,
.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
};
u32 default_init_seq[] = {
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_EM2,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_EM2,
CONFIG_SYS_DDRCMD_EM3,
CONFIG_SYS_DDRCMD_EN_DLL,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_OCD_DEFAULT,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP
};
/*
* fixed sdram init:
* The board doesn't use memory modules that have serial presence
* detect or similar mechanism for discovery of the DRAM settings
*/
long int fixed_sdram(ddr512x_config_t *mddrc_config,
u32 *dram_init_seq, int seq_sz)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
u32 msize_log2 = __ilog2(msize);
u32 i;
/* take default settings and init sequence if necessary */
if (mddrc_config == NULL)
mddrc_config = &default_mddrc_config;
if (dram_init_seq == NULL) {
dram_init_seq = default_init_seq;
seq_sz = ARRAY_SIZE(default_init_seq);
}
/* Initialize IO Control */
out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
/* Initialize DDR Local Window */
out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
sync_law(&im->sysconf.ddrlaw.ar);
/* DDR Enable */
/*
* the "enable" combination: DRAM controller out of reset,
* clock enabled, command mode -- BUT leave CKE low for now
*/
i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
out_be32(&im->mddrc.ddr_sys_config, i);
/* maintain 200 microseconds of stable power and clock */
udelay(200);
/* apply a NOP, it shouldn't harm */
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
/* now assert CKE (high) */
i |= MDDRC_SYS_CFG_CKE_MASK;
out_be32(&im->mddrc.ddr_sys_config, i);
/* Initialize DDR Priority Manager */
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
/*
* Initialize MDDRC
* put MDDRC in CMD mode and
* set the max time between refreshes to 0 during init process
*/
out_be32(&im->mddrc.ddr_sys_config,
mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
out_be32(&im->mddrc.ddr_time_config0,
mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
out_be32(&im->mddrc.ddr_time_config1,
mddrc_config->ddr_time_config1);
out_be32(&im->mddrc.ddr_time_config2,
mddrc_config->ddr_time_config2);
/* Initialize DDR with either default or supplied init sequence */
for (i = 0; i < seq_sz; i++)
out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
/* Start MDDRC */
out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
/* Allow for the DLL to startup before accessing data */
udelay(10);
msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
/* Fix DDR Local Window for new size */
out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
sync_law(&im->sysconf.ddrlaw.ar);
return msize;
}

111
arch/powerpc/cpu/mpc512x/ide.c
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/*
* (C) Copyright 2007-2009 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IDE_RESET)
void ide_set_reset (int idereset)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
debug ("ide_set_reset(%d)\n", idereset);
if (idereset) {
out_be32(&im->pata.pata_ata_control, 0);
} else {
out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
}
udelay(100);
}
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/*
* Clear the reset bit to reset the interface
* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
*/
ide_set_reset(1);
/* Assert the reset bit to enable the interface */
ide_set_reset(0);
}
#define CALC_TIMING(t) (t + period - 1) / period
int ide_preinit (void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
long t;
const struct {
short t0;
short t1;
short t2_8;
short t2_16;
short t2i;
short t4;
short t9;
short tA;
} pio_specs = {
.t0 = 600,
.t1 = 70,
.t2_8 = 290,
.t2_16 = 165,
.t2i = 0,
.t4 = 30,
.t9 = 20,
.tA = 50,
};
union {
u32 config;
struct {
u8 field1;
u8 field2;
u8 field3;
u8 field4;
}bytes;
} cfg;
debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
(u32)&im->pata);
/* Set the reset bit to 1 to enable the interface */
ide_set_reset(0);
/* Init timings : we use PIO mode 0 timings */
t = 1000000000 / gd->arch.ips_clk; /* period in ns */
cfg.bytes.field1 = 3;
cfg.bytes.field2 = 3;
cfg.bytes.field3 = (pio_specs.t1 + t) / t;
cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
out_be32(&im->pata.pata_time1, cfg.config);
cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
cfg.bytes.field3 = 1;
cfg.bytes.field4 = (pio_specs.t4 + t) / t;
out_be32(&im->pata.pata_time2, cfg.config);
cfg.config = in_be32(&im->pata.pata_time3);
cfg.bytes.field1 = (pio_specs.t9 + t) / t;
out_be32(&im->pata.pata_time3, cfg.config);
debug ("PATA preinit complete.\n");
return 0;
}
#endif /* defined(CONFIG_IDE_RESET) */

45
arch/powerpc/cpu/mpc512x/interrupts.c
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/*
* (C) Copyright 2000-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright 2004 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Derived from the MPC83xx code.
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
struct irq_action {
interrupt_handler_t *handler;
void *arg;
ulong count;
};
int interrupt_init_cpu (unsigned *decrementer_count)
{
*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
return 0;
}
/*
* Install and free an interrupt handler.
*/
void
irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
{
}
void irq_free_handler (int irq)
{
}
void timer_interrupt_cpu (struct pt_regs *regs)
{
/* nothing to do here */
return;
}

87
arch/powerpc/cpu/mpc512x/iopin.c
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/*
* (C) Copyright 2008
* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
* mpc512x I/O pin/pad initialization for the ADS5121 board
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
#include <asm/io.h>
void iopin_initialize(iopin_t *ioregs_init, int len)
{
short i, j, p;
u32 *reg;
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
reg = (u32 *)&(im->io_ctrl);
if (sizeof(ioregs_init) == 0)
return;
for (i = 0; i < len; i++) {
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
setbits_be32(reg + j, ioregs_init[i].val);
else
out_be32 (reg + j, ioregs_init[i].val);
}
}
return;
}
void iopin_initialize_bits(iopin_t *ioregs_init, int len)
{
short i, j, p;
u32 *reg, mask;
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
reg = (u32 *)&(im->io_ctrl);
/* iterate over table entries */
for (i = 0; i < len; i++) {
/* iterate over pins within a table entry */
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
/* replace all settings at once */
out_be32(reg + j, ioregs_init[i].val);
} else {
/*
* only replace individual parts, but
* REPLACE them instead of just ORing
* them in and "inheriting" previously
* set bits which we don't want
*/
mask = 0;
if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
mask |= IO_PIN_FMUX(3);
if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
mask |= IO_PIN_HOLD(3);
if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
mask |= IO_PIN_ST(1);
if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
mask |= IO_PIN_DS(3);
/*
* DON'T do the "mask, then insert"
* in place on the register, it may
* break access to external hardware
* (like boot ROMs) when configuring
* LPB related pins, while the code to
* configure the pin is read from this
* very address region
*/
clrsetbits_be32(reg + j, mask,
ioregs_init[i].val & mask);
}
}
}
}

209
arch/powerpc/cpu/mpc512x/pci.c
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/*
* Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
* Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/global_data.h>
#include <pci.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
static struct pci_controller pci_hose;
/**************************************************************************
* pci_init_board()
*
*/
void
pci_init_board(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile law512x_t *pci_law;
volatile pot512x_t *pci_pot;
volatile pcictrl512x_t *pci_ctrl;
u16 reg16;
u32 reg32;
u32 dev;
int i;
struct pci_controller *hose;
/* Set PCI divider for 33MHz */
reg32 = in_be32(&im->clk.scfr[0]);
reg32 &= ~(SCFR1_PCI_DIV_MASK);
reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
out_be32(&im->clk.scfr[0], reg32);
clrsetbits_be32(&im->clk.scfr[0],
SCFR1_PCI_DIV_MASK,
SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
);
pci_law = im->sysconf.pcilaw;
pci_pot = im->ios.pot;
pci_ctrl = &im->pci_ctrl;
hose = &pci_hose;
/*
* Release PCI RST Output signal
*/
out_be32(&pci_ctrl->gcr, 0);
udelay(2000);
out_be32(&pci_ctrl->gcr, 1);
/* We need to wait at least a 1sec based on PCI specs */
for (i = 0; i < 1000; i++)
udelay(1000);
/*
* Configure PCI Local Access Windows
*/
out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
/*
* Configure PCI Outbound Translation Windows
*/
/* PCI mem space - prefetch */
out_be32(&pci_pot[0].potar,
(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[0].pobar,
(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[0].pocmr,
POCMR_EN | POCMR_PRE | POCMR_CM_256M);
/* PCI IO space */
out_be32(&pci_pot[1].potar,
(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[1].pobar,
(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[1].pocmr,
POCMR_EN | POCMR_IO | POCMR_CM_16M);
/* PCI mmio - non-prefetch mem space */
out_be32(&pci_pot[2].potar,
(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[2].pobar,
(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[2].pocmr,
POCMR_EN | POCMR_CM_256M);
/*
* Configure PCI Inbound Translation Windows
*/
/* we need RAM mapped to PCI space for the devices to
* access main memory */
out_be32(&pci_ctrl[0].pitar1, 0x0);
out_be32(&pci_ctrl[0].pibar1, 0x0);
out_be32(&pci_ctrl[0].piebar1, 0x0);
out_be32(&pci_ctrl[0].piwar1,
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
hose->first_busno = 0;
hose->last_busno = 0xff;
/* PCI memory prefetch space */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEM_BASE,
CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE,
PCI_REGION_MEM|PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CONFIG_SYS_PCI_MMIO_BASE,
CONFIG_SYS_PCI_MMIO_PHYS,
CONFIG_SYS_PCI_MMIO_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 2,
CONFIG_SYS_PCI_IO_BASE,
CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE,
PCI_REGION_IO);
/* System memory space */
pci_set_region(hose->regions + 3,
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
pci_setup_indirect(hose,
(CONFIG_SYS_IMMR + 0x8300),
(CONFIG_SYS_IMMR + 0x8304));
pci_register_hose(hose);
/*
* Write to Command register
*/
reg16 = 0xff;
dev = PCI_BDF(hose->first_busno, 0, 0);
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
}
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
path = fdt_getprop(blob, nodeoffset, "pci", NULL);
if (path) {
tmp[0] = cpu_to_be32(pci_hose.first_busno);
tmp[1] = cpu_to_be32(pci_hose.last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
tmp[0] = cpu_to_be32(gd->pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
}
}
#endif /* CONFIG_OF_LIBFDT */

431
arch/powerpc/cpu/mpc512x/serial.c
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/*
* (C) Copyright 2000 - 2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Based ont the MPC5200 PSC driver.
* Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
*/
/*
* Minimal serial functions needed to use one of the PSC ports
* as serial console interface.
*/
#include <common.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PSC_CONSOLE)
static void fifo_init (volatile psc512x_t *psc)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 tfsize, rfsize;
/* reset Rx & Tx fifo slice */
out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
/* disable Tx & Rx FIFO interrupts */
out_be32(&psc->rfintmask, 0);
out_be32(&psc->tfintmask, 0);
switch (((u32)psc & 0xf00) >> 8) {
case 0:
tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
break;
case 1:
tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
break;
case 2:
tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
break;
case 3:
tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
break;
case 4:
tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
break;
case 5:
tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
break;
case 6:
tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
break;
case 7:
tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
break;
case 8:
tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
break;
case 9:
tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
break;
case 10:
tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
break;
case 11:
tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
break;
default:
return;
}
out_be32(&psc->tfsize, tfsize);
out_be32(&psc->rfsize, rfsize);
/* enable Tx & Rx FIFO slice */
out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
__asm__ volatile ("sync");
}
void serial_setbrg_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
unsigned long baseclk, div;
unsigned long baudrate;
char buf[16];
char *br_env;
baudrate = gd->baudrate;
if (idx != CONFIG_PSC_CONSOLE) {
/* Allows setting baudrate for other serial devices
* on PSCx using environment. If not specified, use
* the same baudrate as for console.
*/
sprintf(buf, "psc%d_baudrate", idx);
br_env = getenv(buf);
if (br_env)
baudrate = simple_strtoul(br_env, NULL, 10);
debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
}
/* calculate divisor for setting PSC CTUR and CTLR registers */
baseclk = (gd->arch.ips_clk + 8) / 16;
div = (baseclk + (baudrate / 2)) / baudrate;
out_8(&psc->ctur, (div >> 8) & 0xff);
out_8(&psc->ctlr, div & 0xff); /* set baudrate */
}
int serial_init_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
u32 reg;
reg = in_be32(&im->clk.sccr[0]);
out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
fifo_init (psc);
/* set MR register to point to MR1 */
out_8(&psc->command, PSC_SEL_MODE_REG_1);
/* disable Tx/Rx */
out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
/* choose the prescaler by 16 for the Tx/Rx clock generation */
out_be16(&psc->psc_clock_select, 0xdd00);
/* switch to UART mode */
out_be32(&psc->sicr, 0);
/* mode register points to mr1 */
/* configure parity, bit length and so on in mode register 1*/
out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
/* now, mode register points to mr2 */
out_8(&psc->mode, PSC_MODE_1_STOPBIT);
/* set baudrate */
serial_setbrg_dev(idx);
/* disable all interrupts */
out_be16(&psc->psc_imr, 0);
/* reset and enable Rx/Tx */
out_8(&psc->command, PSC_RST_RX);
out_8(&psc->command, PSC_RST_TX);
out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
return 0;
}
int serial_uninit_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
u32 reg;
out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
reg = in_be32(&im->clk.sccr[0]);
reg &= ~CLOCK_SCCR1_PSC_EN(idx);
out_be32(&im->clk.sccr[0], reg);
return 0;
}
void serial_putc_dev(unsigned int idx, const char c)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
if (c == '\n')
serial_putc_dev(idx, '\r');
/* Wait for last character to go. */
while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
;
out_8(&psc->tfdata_8, c);
}
void serial_puts_dev(unsigned int idx, const char *s)
{
while (*s)
serial_putc_dev(idx, *s++);
}
int serial_getc_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
/* Wait for a character to arrive. */
while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
;
return in_8(&psc->rfdata_8);
}
int serial_tstc_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
}
void serial_setrts_dev(unsigned int idx, int s)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
if (s) {
/* Assert RTS (become LOW) */
out_8(&psc->op1, 0x1);
}
else {
/* Negate RTS (become HIGH) */
out_8(&psc->op0, 0x1);
}
}
int serial_getcts_dev(unsigned int idx)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
return (in_8(&psc->ip) & 0x1) ? 0 : 1;
}
#endif /* CONFIG_PSC_CONSOLE */
#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
int serial##port##_init(void) \
{ \
return serial_init_dev(port); \
} \
int serial##port##_uninit(void) \
{ \
return serial_uninit_dev(port); \
} \
void serial##port##_setbrg(void) \
{ \
serial_setbrg_dev(port); \
} \
int serial##port##_getc(void) \
{ \
return serial_getc_dev(port); \
} \
int serial##port##_tstc(void) \
{ \
return serial_tstc_dev(port); \
} \
void serial##port##_putc(const char c) \
{ \
serial_putc_dev(port, c); \
} \
void serial##port##_puts(const char *s) \
{ \
serial_puts_dev(port, s); \
}
#define INIT_PSC_SERIAL_STRUCTURE(port, __name) { \
.name = __name, \
.start = serial##port##_init, \
.stop = serial##port##_uninit, \
.setbrg = serial##port##_setbrg, \
.getc = serial##port##_getc, \
.tstc = serial##port##_tstc, \
.putc = serial##port##_putc, \
.puts = serial##port##_puts, \
}
#if defined(CONFIG_SYS_PSC1)
DECLARE_PSC_SERIAL_FUNCTIONS(1);
struct serial_device serial1_device =
INIT_PSC_SERIAL_STRUCTURE(1, "psc1");
#endif
#if defined(CONFIG_SYS_PSC3)
DECLARE_PSC_SERIAL_FUNCTIONS(3);
struct serial_device serial3_device =
INIT_PSC_SERIAL_STRUCTURE(3, "psc3");
#endif
#if defined(CONFIG_SYS_PSC4)
DECLARE_PSC_SERIAL_FUNCTIONS(4);
struct serial_device serial4_device =
INIT_PSC_SERIAL_STRUCTURE(4, "psc4");
#endif
#if defined(CONFIG_SYS_PSC6)
DECLARE_PSC_SERIAL_FUNCTIONS(6);
struct serial_device serial6_device =
INIT_PSC_SERIAL_STRUCTURE(6, "psc6");
#endif
__weak struct serial_device *default_serial_console(void)
{
#if (CONFIG_PSC_CONSOLE == 3)
return &serial3_device;
#elif (CONFIG_PSC_CONSOLE == 6)
return &serial6_device;
#else
#error "invalid CONFIG_PSC_CONSOLE"
#endif
}
void mpc512x_serial_initialize(void)
{
#if defined(CONFIG_SYS_PSC1)
serial_register(&serial1_device);
#endif
#if defined(CONFIG_SYS_PSC3)
serial_register(&serial3_device);
#endif
#if defined(CONFIG_SYS_PSC4)
serial_register(&serial4_device);
#endif
#if defined(CONFIG_SYS_PSC6)
serial_register(&serial6_device);
#endif
}
#include <stdio_dev.h>
/*
* Routines for communication with serial devices over PSC
*/
/* Bitfield for initialized PSCs */
static unsigned int initialized;
struct stdio_dev *open_port(int num, int baudrate)
{
struct stdio_dev *port;
char env_var[16];
char env_val[10];
char name[7];
if (num < 0 || num > 11)
return NULL;
sprintf(name, "psc%d", num);
port = stdio_get_by_name(name);
if (!port)
return NULL;
if (!test_bit(num, &initialized)) {
sprintf(env_var, "psc%d_baudrate", num);
sprintf(env_val, "%d", baudrate);
setenv(env_var, env_val);
if (port->start(port))
return NULL;
set_bit(num, &initialized);
}
return port;
}
int close_port(int num)
{
struct stdio_dev *port;
int ret;
char name[7];
if (num < 0 || num > 11)
return -1;
sprintf(name, "psc%d", num);
port = stdio_get_by_name(name);
if (!port)
return -1;
ret = port->stop(port);
clear_bit(num, &initialized);
return ret;
}
int write_port(struct stdio_dev *port, char *buf)
{
if (!port || !buf)
return -1;
port->puts(port, buf);
return 0;
}
int read_port(struct stdio_dev *port, char *buf, int size)
{
int cnt = 0;
if (!port || !buf)
return -1;
if (!size)
return 0;
while (port->tstc(port)) {
buf[cnt++] = port->getc(port);
if (cnt > size)
break;
}
return cnt;
}

137
arch/powerpc/cpu/mpc512x/speed.c
View File

@ -1,137 +0,0 @@
/*
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Based on the MPC83xx code.
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
static int spmf_mult[] = {
68, 1, 12, 16,
20, 24, 28, 32,
36, 40, 44, 48,
52, 56, 60, 64
};
static int cpmf_mult[][2] = {
{0, 1}, {0, 1}, /* 0 and 1 are not valid */
{1, 1}, {3, 2},
{2, 1}, {5, 2},
{3, 1}, {7, 2},
{0, 1}, {0, 1}, /* and all above 7 are not valid too */
{0, 1}, {0, 1},
{0, 1}, {0, 1},
{0, 1}, {0, 1}
};
static int sys_dividors[][2] = {
{2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
{9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
{9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
{15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
{18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
{24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
{29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
};
int get_clocks (void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf;
u8 cpmf;
u8 sys_div;
u8 ips_div;
u8 pci_div;
u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
u32 spll;
u32 sys_clk;
u32 core_clk;
u32 csb_clk;
u32 ips_clk;
u32 pci_clk;
u32 reg;
reg = in_be32(&im->sysconf.immrbar);
if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
reg = in_be32(&im->clk.spmr);
spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
reg = in_be32(&im->clk.scfr[1]);
sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
reg = in_be32(&im->clk.spmr);
cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
reg = in_be32(&im->clk.scfr[0]);
ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
ips_clk = csb_clk / ips_div;
} else {
/* in case we cannot get a sane IPS divisor, fail gracefully */
ips_clk = 0;
}
reg = in_be32(&im->clk.scfr[0]);
pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
if (pci_div != 0) {
pci_clk = csb_clk / pci_div;
} else {
/* in case we cannot get a sane IPS divisor, fail gracefully */
pci_clk = 333333;
}
gd->arch.ips_clk = ips_clk;
gd->pci_clk = pci_clk;
gd->arch.csb_clk = csb_clk;
gd->cpu_clk = core_clk;
gd->bus_clk = csb_clk;
return 0;
}
/********************************************
* get_bus_freq
* return system bus freq in Hz
*********************************************/
ulong get_bus_freq (ulong dummy)
{
return gd->arch.csb_clk;
}
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
char buf[32];
printf("Clock configuration:\n");
printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
printf(" Coherent System Bus: %-4s MHz\n",
strmhz(buf, gd->arch.csb_clk));
printf(" IPS Bus: %-4s MHz\n",
strmhz(buf, gd->arch.ips_clk));
printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
printf(" DDR: %-4s MHz\n",
strmhz(buf, 2 * gd->arch.csb_clk));
return 0;
}
U_BOOT_CMD(clocks, 1, 0, do_clocks,
"print clock configuration",
" clocks"
);

694
arch/powerpc/cpu/mpc512x/start.S
View File

@ -1,694 +0,0 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
* Copyright Freescale Semiconductor, Inc. 2004, 2006.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Based on the MPC83xx code.
*/
/*
* U-Boot - Startup Code for MPC512x based Embedded Boards
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
#include <asm/immap_512x.h>
#include "asm-offsets.h"
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>
/*
* Floating Point enable, Machine Check and Recoverable Interr.
*/
#undef MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
/* Macros for manipulating CSx_START/STOP */
#define START_REG(start) ((start) >> 16)
#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
/*
* Magic number and version string
*/
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
/*
* Vector Table
*/
.text
. = EXC_OFF_SYS_RESET
.globl _start
/* Start from here after reset/power on */
_start:
b boot_cold
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
/* Floating Point Unit unavailable exception */
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* Decrementer */
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
/* Critical interrupt */
STD_EXCEPTION(0xa00, Critical, UnknownException)
/* System Call */
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
/* Trace interrupt */
STD_EXCEPTION(0xd00, Trace, UnknownException)
/* Performance Monitor interrupt */
STD_EXCEPTION(0xf00, PerfMon, UnknownException)
/* Intruction Translation Miss */
STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
/* Data Load Translation Miss */
STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
/* Data Store Translation Miss */
STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
/* Instruction Address Breakpoint */
STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
/* System Management interrupt */
STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x3000
boot_cold:
/* Save msr contents */
mfmsr r5
/* Set IMMR area to our preferred location */
lis r4, CONFIG_DEFAULT_IMMR@h
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
stw r3, IMMRBAR(r4)
mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
/* Initialise the machine */
bl cpu_early_init
/*
* Set up Local Access Windows:
*
* 1) Boot/CS0 (boot FLASH)
* 2) On-chip SRAM (initial stack purposes)
*/
/* Boot CS/CS0 window range */
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
stw r4, LPCS0AW(r3)
/*
* The SRAM window has a fixed size (256K), so only the start address
* is necessary
*/
lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
stw r4, SRAMBAR(r3)
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync
*/
lwz r4, SRAMBAR(r3)
isync
/*
* Set configuration of the Boot/CS0, the SRAM window does not have a
* config register so no params can be set for it
*/
lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
lis r4, CONFIG_SYS_CS0_CFG@h
ori r4, r4, CONFIG_SYS_CS0_CFG@l
stw r4, CS0_CONFIG(r3)
/* Master enable all CS's */
lis r4, CS_CTRL_ME@h
ori r4, r4, CS_CTRL_ME@l
stw r4, CS_CTRL(r3)
lis r4, (CONFIG_SYS_MONITOR_BASE)@h
ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r5
blr
in_flash:
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable & stack humble */
/*------------------------------------------------------*/
GET_GOT /* initialize GOT access */
/* r3: IMMR */
lis r3, CONFIG_SYS_IMMR@h
/* run low-level CPU init code (in Flash) */
bl cpu_init_f
/* run 1st part of board init code (in Flash) */
bl board_init_f
/* NOTREACHED - board_init_f() does not return */
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
/*
* This code initialises the machine, it expects original MSR contents to be in r5.
*/
cpu_early_init:
/* Initialize machine status; enable machine check interrupt */
/*-----------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME and RI flags */
rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
#ifdef DEBUG
rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
#endif
mtmsr r3
SYNC
mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
/* Initialise the watchdog and reset it */
/*--------------------------------------*/
lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3)
/* reset */
li r4, 0x556C
sth r4, SWSRR@l(r3)
li r4, 0x0
ori r4, r4, 0xAA39
sth r4, SWSRR@l(r3)
#else
/* Disable the watchdog */
/*----------------------*/
lwz r4, SWCRR(r3)
/*
* Check to see if it's enabled for disabling: once disabled by s/w
* it's not possible to re-enable it
*/
andi. r4, r4, 0x4
beq 1f
xor r4, r4, r4
stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
/*------------------------------------------------------*/
lis r3, CONFIG_SYS_HID0_INIT@h
ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
lis r3, CONFIG_SYS_HID0_FINAL@h
ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
lis r3, CONFIG_SYS_HID2@h
ori r3, r3, CONFIG_SYS_HID2@l
SYNC
mtspr HID2, r3
sync
blr
/* Cache functions.
*
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
.globl icache_enable
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
lis r4, 0
ori r4, r4, HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_disable
icache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_ICE|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_status
icache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
.globl dcache_enable
dcache_enable:
mfspr r3, HID0
li r5, HID0_DCFI|HID0_DLOCK
andc r3, r3, r5
mtspr HID0, r3 /* no invalidate, unlock */
ori r3, r3, HID0_DCE
ori r5, r3, HID0_DCFI
mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */
sync
blr
.globl dcache_disable
dcache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_DCE|HID0_DLOCK
andc r3, r3, r4
ori r4, r3, HID0_DCI
sync
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_status
dcache_status:
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
blr
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
.globl get_svr
get_svr:
mfspr r3, SVR
blr
/*-------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
GET_GOT
mr r3, r5 /* Destination Address */
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
* + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r12, r12, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
/* copy */
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
addi r0,r5,3
srwi. r0,r0,2
mtctr r0
la r8,-4(r4)
la r7,-4(r3)
/* and compare */
20: lwzu r20,4(r8)
lwzu r21,4(r7)
xor. r22, r20, r21
bne 30f
bdnz 20b
b 4f
/* compare failed */
30: li r3, 0
blr
2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mfmsr r3 /* now that the vectors have */
lis r7, MSR_IP@h /* relocated into low memory */
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
andc r3, r3, r7 /* (if it was on) */
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtlr r4 /* restore link register */
blr

190
arch/powerpc/cpu/mpc512x/traps.c
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@ -1,190 +0,0 @@
/*
* (C) Copyright 2000 - 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* SPDX-License-Identifier: GPL-2.0+
*
* Derived from the MPC83xx code.
*/
/*
* This file handles the architecture-dependent parts of hardware
* exceptions
*/
#include <common.h>
#include <kgdb.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long search_exception_table(unsigned long);
/*
* End of addressable memory. This may be less than the actual
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
/*
* Trap & Exception support
*/
static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
puts("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
putc('\n');
printf("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *) *sp;
}
putc('\n');
}
void show_regs(struct pt_regs *regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
regs->msr & MSR_IR ? 1 : 0,
regs->msr & MSR_DR ? 1 : 0);
putc('\n');
for (i = 0; i < 32; i++) {
if ((i % 8) == 0) {
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7) {
putc('\n');
}
}
}
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception at pc %lx signal %d", regs->nip, signr);
}
void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup = search_exception_table(regs->nip);
if (fixup) {
regs->nip = fixup;
return;
}
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
puts("Machine check.\nCaused by (from msr): ");
printf("regs %p ", regs);
switch (regs->msr & 0x00FF0000) {
case (0x80000000 >> 10):
puts("Instruction cache parity signal\n");
break;
case (0x80000000 >> 11):
puts("Data cache parity signal\n");
break;
case (0x80000000 >> 12):
puts("Machine check signal\n");
break;
case (0x80000000 >> 13):
puts("Transfer error ack signal\n");
break;
case (0x80000000 >> 14):
puts("Data parity signal\n");
break;
case (0x80000000 >> 15):
puts("Address parity signal\n");
break;
default:
puts("Unknown values in msr\n");
}
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");
}
void AlignmentException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Alignment Exception");
}
void ProgramCheckException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
}
void SoftEmuException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Software Emulation Exception");
}
void UnknownException(struct pt_regs *regs)
{
#ifdef CONFIG_CMD_KGDB
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
#ifdef CONFIG_CMD_BEDBUG
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip);
show_regs(regs);
#ifdef CONFIG_CMD_BEDBUG
do_bedbug_breakpoint(regs);
#endif
}

73
arch/powerpc/cpu/mpc512x/u-boot.lds
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@ -1,73 +0,0 @@
/*
* (C) Copyright 2007-2010 DENX Software Engineering.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
.text :
{
arch/powerpc/cpu/mpc512x/start.o (.text*)
*(.text*)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
*(.fixup)
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)

90
arch/powerpc/cpu/mpc5xxx/Kconfig
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@ -1,90 +0,0 @@
menu "mpc5xxx CPU"
depends on MPC5xxx
config SYS_CPU
default "mpc5xxx"
choice
prompt "Target select"
optional
config TARGET_A3M071
bool "Support a3m071"
select SUPPORT_SPL
config TARGET_A4M072
bool "Support a4m072"
config TARGET_CANMB
bool "Support canmb"
config TARGET_CM5200
bool "Support cm5200"
config TARGET_INKA4X0
bool "Support inka4x0"
config TARGET_IPEK01
bool "Support ipek01"
config TARGET_JUPITER
bool "Support jupiter"
config TARGET_MOTIONPRO
bool "Support motionpro"
config TARGET_MUNICES
bool "Support munices"
config TARGET_V38B
bool "Support v38b"
config TARGET_O2D
bool "Support O2D"
config TARGET_O2D300
bool "Support O2D300"
config TARGET_O2DNT2
bool "Support O2DNT2"
config TARGET_O2I
bool "Support O2I"
config TARGET_O2MNT
bool "Support O2MNT"
config TARGET_O3DNT
bool "Support O3DNT"
config TARGET_DIGSY_MTC
bool "Support digsy_mtc"
imply CMD_IRQ
config TARGET_PCM030
bool "Support pcm030"
config TARGET_CHARON
bool "Support charon"
config TARGET_TQM5200
bool "Support TQM5200"
endchoice
source "board/a3m071/Kconfig"
source "board/a4m072/Kconfig"
source "board/canmb/Kconfig"
source "board/cm5200/Kconfig"
source "board/ifm/o2dnt2/Kconfig"
source "board/inka4x0/Kconfig"
source "board/intercontrol/digsy_mtc/Kconfig"
source "board/ipek01/Kconfig"
source "board/jupiter/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
source "board/tqc/tqm5200/Kconfig"
source "board/v38b/Kconfig"
endmenu

25
arch/powerpc/cpu/mpc5xxx/Makefile
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@ -1,25 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y = start.o
extra-y += traps.o
obj-y += io.o
obj-y += firmware_sc_task_bestcomm.impl.o
obj-y += cpu.o
obj-y += cpu_init.o
obj-y += ide.o
obj-y += interrupts.o
obj-y += loadtask.o
obj-y += pci_mpc5200.o
obj-y += serial.o
obj-y += speed.o
obj-$(CONFIG_CMD_USB) += usb_ohci.o
obj-$(CONFIG_CMD_USB) += usb.o
ifdef CONFIG_SPL_BUILD
obj-y += spl_boot.o
endif

8
arch/powerpc/cpu/mpc5xxx/config.mk
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@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple

168
arch/powerpc/cpu/mpc5xxx/cpu.c
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@ -1,168 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* CPU specific code for the MPC5xxx CPUs
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <net.h>
#include <mpc5xxx.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
#if defined(CONFIG_OF_IDE_FIXUP)
#include <ide.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkcpu (void)
{
ulong clock = gd->cpu_clk;
char buf[32];
uint svr, pvr;
puts ("CPU: ");
svr = get_svr();
pvr = get_pvr();
switch (pvr) {
case PVR_5200:
printf("MPC5200");
break;
case PVR_5200B:
printf("MPC5200B");
break;
default:
printf("Unknown MPC5xxx");
break;
}
printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
PVR_MAJ(pvr), PVR_MIN(pvr));
printf (" at %s MHz\n", strmhz (buf, clock));
return 0;
}
/* ------------------------------------------------------------------------- */
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
ulong msr;
/* Interrupts and MMU off */
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
/* Charge the watchdog timer */
*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
while(1);
return 1;
}
/* ------------------------------------------------------------------------- */
/*
* Get timebase clock frequency (like cpu_clk in Hz)
*
*/
unsigned long get_tbclk (void)
{
ulong tbclk;
tbclk = (gd->bus_clk + 3L) / 4L;
return (tbclk);
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_OF_BOARD_SETUP
void ft_cpu_setup(void *blob, bd_t *bd)
{
int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
#ifdef CONFIG_MPC5xxx_FEC
uchar enetaddr[6];
char * eth_path = "/" OF_SOC "/ethernet@3000";
#endif
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
bd->bi_busfreq*div, 1);
#ifdef CONFIG_MPC5xxx_FEC
eth_getenv_enetaddr("ethaddr", enetaddr);
do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
#endif
#ifdef CONFIG_OF_IDE_FIXUP
if (!ide_device_present(0)) {
/* NO CF card detected -> delete ata node in DTS */
int nodeoffset = 0;
char nodename[] = "/soc5200@f0000000/ata@3a00";
nodeoffset = fdt_path_offset(blob, nodename);
if (nodeoffset >= 0) {
fdt_del_node(blob, nodeoffset);
} else {
printf("%s: cannot find %s node err:%s\n",
__func__, nodename, fdt_strerror(nodeoffset));
}
}
#endif /* CONFIG_OF_IDE_FIXUP */
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_MPC5xxx_FEC
/* Default initializations for FEC controllers. To override,
* create a board-specific function called:
* int board_eth_init(bd_t *bis)
*/
int cpu_eth_init(bd_t *bis)
{
return mpc5xxx_fec_initialize(bis);
}
#endif
#if defined(CONFIG_WATCHDOG)
void watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_5xxx_watchdog();
if (re_enable) enable_interrupts();
}
void reset_5xxx_watchdog(void)
{
volatile struct mpc5xxx_gpt *gpt0 =
(struct mpc5xxx_gpt *) MPC5XXX_GPT;
/* Trigger TIMER_0 by writing A5 to OCPW */
clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
}
#endif /* CONFIG_WATCHDOG */

231
arch/powerpc/cpu/mpc5xxx/cpu_init.c
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@ -1,231 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <asm/io.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers.
*/
void cpu_init_f (void)
{
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
volatile struct mpc5xxx_lpb *lpb =
(struct mpc5xxx_lpb *) MPC5XXX_LPB;
volatile struct mpc5xxx_gpio *gpio =
(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
volatile struct mpc5xxx_xlb *xlb =
(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
volatile struct mpc5xxx_cdm *cdm =
(struct mpc5xxx_cdm *) MPC5XXX_CDM;
#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
#if defined(CONFIG_WATCHDOG)
volatile struct mpc5xxx_gpt *gpt0 =
(struct mpc5xxx_gpt *) MPC5XXX_GPT;
#endif /* CONFIG_WATCHDOG */
unsigned long addecr = (1 << 25); /* Boot_CS */
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/*
* Memory Controller: configure chip selects and enable them
*/
#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
CONFIG_SYS_BOOTCS_SIZE));
#endif
#if defined(CONFIG_SYS_BOOTCS_CFG)
out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
#endif
#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
CONFIG_SYS_CS0_SIZE));
/* CS0 and BOOT_CS cannot be enabled at once. */
/* addecr |= (1 << 16); */
#endif
#if defined(CONFIG_SYS_CS0_CFG)
out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
#endif
#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
CONFIG_SYS_CS1_SIZE));
addecr |= (1 << 17);
#endif
#if defined(CONFIG_SYS_CS1_CFG)
out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
#endif
#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
CONFIG_SYS_CS2_SIZE));
addecr |= (1 << 18);
#endif
#if defined(CONFIG_SYS_CS2_CFG)
out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
#endif
#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
CONFIG_SYS_CS3_SIZE));
addecr |= (1 << 19);
#endif
#if defined(CONFIG_SYS_CS3_CFG)
out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
#endif
#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
CONFIG_SYS_CS4_SIZE));
addecr |= (1 << 20);
#endif
#if defined(CONFIG_SYS_CS4_CFG)
out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
#endif
#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
CONFIG_SYS_CS5_SIZE));
addecr |= (1 << 21);
#endif
#if defined(CONFIG_SYS_CS5_CFG)
out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
#endif
addecr |= 1;
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
CONFIG_SYS_CS6_SIZE));
addecr |= (1 << 26);
#endif
#if defined(CONFIG_SYS_CS6_CFG)
out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
#endif
#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
CONFIG_SYS_CS7_SIZE));
addecr |= (1 << 27);
#endif
#if defined(CONFIG_SYS_CS7_CFG)
out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
#endif
#if defined(CONFIG_SYS_CS_BURST)
out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
#endif
#if defined(CONFIG_SYS_CS_DEADCYCLE)
out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
#endif
/* Enable chip selects */
out_be32(&mm->ipbi_ws_ctrl, addecr);
out_be32(&lpb->cs_ctrl, (1 << 24));
/* Setup pin multiplexing */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif
/* Setup gpios */
#if defined(CONFIG_SYS_GPIO_DATADIR)
out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
#endif
#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
#endif
#if defined(CONFIG_SYS_GPIO_DATAVALUE)
out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
#endif
#if defined(CONFIG_SYS_GPIO_ENABLE)
out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
#endif
/* enable timebase */
setbits_be32(&xlb->config, (1 << 13));
/* Enable snooping for RAM */
setbits_be32(&xlb->config, (1 << 15));
out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
setbits_be32(&mm->ipbi_ws_ctrl, 1);
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = in_be32(&cdm->cfg);
addecr &= ~0x103;
# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
out_be32(&cdm->cfg, addecr);
#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
out_be32(&xlb->master_pri_enable, 0xff);
out_be32(&xlb->master_priority, 0x11111111);
#if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */
clrbits_be32(&xlb->config, (1 << 31));
#endif
#if defined(CONFIG_WATCHDOG)
/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
out_be32(&gpt0->cir, 0x0000ffff);
out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */
reset_5xxx_watchdog();
#endif /* CONFIG_WATCHDOG */
}
/*
* initialize higher level parts of CPU like time base and timers
*/
int cpu_init_r (void)
{
volatile struct mpc5xxx_intr *intr =
(struct mpc5xxx_intr *) MPC5XXX_ICTL;
/* mask all interrupts */
out_be32(&intr->per_mask, 0xffffff00);
setbits_be32(&intr->main_mask, 0x0001ffff);
clrbits_be32(&intr->ctrl, 0x00000f00);
/* route critical ints to normal ints */
setbits_be32(&intr->ctrl, 0x00000001);
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
/* load FEC microcode */
loadtask(0, 2);
#endif
return (0);
}

359
arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
View File

@ -1,359 +0,0 @@
/*
* Copyright (C) 2001, Software Center, Motorola China.
*
* This file contains microcode for the FEC controller of the MPC5200 CPU.
*/
#include <config.h>
/* sas/sccg, gas target */
.section smartdmaInitData,"aw",@progbits /* Initialized data for task variables */
.section smartdmaTaskTable,"aw",@progbits /* Task tables */
.align 9
.globl taskTable
taskTable:
.globl scEthernetRecv_Entry
scEthernetRecv_Entry: /* Task 0 */
.long scEthernetRecv_TDT - taskTable /* Task 0 Descriptor Table */
.long scEthernetRecv_TDT - taskTable + 0x000000a4
.long scEthernetRecv_VarTab - taskTable /* Task 0 Variable Table */
.long scEthernetRecv_FDT - taskTable + 0x03 /* Task 0 Function Descriptor Table & Flags */
.long 0x00000000
.long 0x00000000
.long scEthernetRecv_CSave - taskTable /* Task 0 context save space */
.long CONFIG_SYS_MBAR
.globl scEthernetXmit_Entry
scEthernetXmit_Entry: /* Task 1 */
.long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */
.long scEthernetXmit_TDT - taskTable + 0x000000d0
.long scEthernetXmit_VarTab - taskTable /* Task 1 Variable Table */
.long scEthernetXmit_FDT - taskTable + 0x03 /* Task 1 Function Descriptor Table & Flags */
.long 0x00000000
.long 0x00000000
.long scEthernetXmit_CSave - taskTable /* Task 1 context save space */
.long CONFIG_SYS_MBAR
.globl scEthernetRecv_TDT
scEthernetRecv_TDT: /* Task 0 Descriptor Table */
.long 0xc4c50000 /* 0000: LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
.long 0x84c5e000 /* 0004: LCD: idx1 = var9 + var11; ; idx1 += inc0 */
.long 0x10001f08 /* 0008: DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x10000380 /* 000C: DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x00000f88 /* 0010: DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
.long 0x010cf04c /* 0020: DRD2B1: var4 = EU3(); EU3(var1,var12) */
.long 0x82180349 /* 0024: LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
.long 0x81c68004 /* 0028: LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
.long 0x70000000 /* 002C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x018cf04e /* 0030: DRD2B1: var6 = EU3(); EU3(var1,var14) */
.long 0x70000000 /* 0034: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x020cf04f /* 0038: DRD2B1: var8 = EU3(); EU3(var1,var15) */
.long 0x00000b88 /* 003C: DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
.long 0x8000d184 /* 0040: LCDEXT: idx1 = 0xf0003184; ; */
.long 0xc6990452 /* 0044: LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
.long 0x81486010 /* 0048: LCD: idx3 = var2 + var16; ; idx3 += inc2 */
.long 0x006acf88 /* 004C: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
.long 0x8000d184 /* 0050: LCDEXT: idx1 = 0xf0003184; ; */
.long 0x86810492 /* 0054: LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
.long 0x006acf88 /* 0058: DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
.long 0x8000d184 /* 005C: LCDEXT: idx1 = 0xf0003184; ; */
.long 0x868184d2 /* 0060: LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
.long 0x000acf88 /* 0064: DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
.long 0xc318839b /* 0068: LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
.long 0x80190000 /* 006C: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
.long 0x04008468 /* 0070: DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
.long 0xc4038358 /* 0074: LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
.long 0x81c50000 /* 0078: LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
.long 0x1000cb18 /* 007C: DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x00000f18 /* 0080: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
.long 0xc4188364 /* 0084: LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
.long 0x83990000 /* 0088: LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
.long 0x10000c00 /* 008C: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x0000c800 /* 0090: DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
.long 0x81988000 /* 0094: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
.long 0x10000788 /* 0098: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x60000000 /* 009C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
.long 0x080cf04c /* 00A0: DRD2B1: idx0 = EU3(); EU3(var1,var12) */
.long 0x000001f8 /* 00A4(:0): NOP */
.globl scEthernetXmit_TDT
scEthernetXmit_TDT: /* Task 1 Descriptor Table */
.long 0x80024800 /* 0000: LCDEXT: idx0 = 0xf0008800; ; */
.long 0x85c60004 /* 0004: LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
.long 0x10002308 /* 0008: DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x10000f88 /* 000C: DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x00000380 /* 0010: DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
.long 0x81980000 /* 0014: LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
.long 0x10000780 /* 0018: DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x60000000 /* 001C: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
.long 0x024cf04d /* 0020: DRD2B1: var9 = EU3(); EU3(var1,var13) */
.long 0x84980309 /* 0024: LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
.long 0xc0004003 /* 0028: LCDEXT: idx1 = 0x00000003; ; */
.long 0x81c60004 /* 002C: LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
.long 0x70000000 /* 0030: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x010cf04e /* 0034: DRD2B1: var4 = EU3(); EU3(var1,var14) */
.long 0x70000000 /* 0038: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x014cf04f /* 003C: DRD2B1: var5 = EU3(); EU3(var1,var15) */
.long 0x70000000 /* 0040: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x028cf050 /* 0044: DRD2B1: var10 = EU3(); EU3(var1,var16) */
.long 0x70000000 /* 0048: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
.long 0x018cf051 /* 004C: DRD2B1: var6 = EU3(); EU3(var1,var17) */
.long 0x10000b90 /* 0050: DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x60000000 /* 0054: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
.long 0x01ccf0a1 /* 0058: DRD2B1: var7 = EU3(); EU3(var2,idx1) */
.long 0xc2988312 /* 005C: LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
.long 0x83490000 /* 0060: LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
.long 0x00001b10 /* 0064: DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
.long 0x8000d1a4 /* 0068: LCDEXT: idx1 = 0xf00031a4; ; */
.long 0x8301031c /* 006C: LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
.long 0x008ac798 /* 0070: DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
.long 0x8000d1a4 /* 0074: LCDEXT: idx1 = 0xf00031a4; ; */
.long 0xc1430000 /* 0078: LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
.long 0x82998312 /* 007C: LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
.long 0x088ac790 /* 0080: DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
.long 0x81988000 /* 0084: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
.long 0x60000001 /* 0088: DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */
.long 0x0c4cfc4d /* 008C: DRD2B1: *idx1 = EU3(); EU3(*idx1,var13) */
.long 0xc21883ad /* 0090: LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
.long 0x80190000 /* 0094: LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
.long 0x04008460 /* 0098: DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
.long 0xc4052305 /* 009C: LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
.long 0x81c98000 /* 00A0: LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
.long 0x1000c718 /* 00A4: DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x00000f18 /* 00A8: DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
.long 0xc4188000 /* 00AC: LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
.long 0x85190312 /* 00B0: LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
.long 0x10000c00 /* 00B4: DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x1000c400 /* 00B8: DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x00008860 /* 00BC: DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
.long 0x81988000 /* 00C0: LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
.long 0x10000788 /* 00C4: DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
.long 0x60000000 /* 00C8: DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
.long 0x080cf04d /* 00CC: DRD2B1: idx0 = EU3(); EU3(var1,var13) */
.long 0x000001f8 /* 00D0(:0): NOP */
.align 8
.globl scEthernetRecv_VarTab
scEthernetRecv_VarTab: /* Task 0 Variable Table */
.long 0x00000000 /* var[0] */
.long 0x00000000 /* var[1] */
.long 0x00000000 /* var[2] */
.long 0x00000000 /* var[3] */
.long 0x00000000 /* var[4] */
.long 0x00000000 /* var[5] */
.long 0x00000000 /* var[6] */
.long 0x00000000 /* var[7] */
.long 0x00000000 /* var[8] */
.long (CONFIG_SYS_MBAR + 0x8800) /* var[9] */
.long 0x00000008 /* var[10] */
.long 0x0000000c /* var[11] */
.long 0x80000000 /* var[12] */
.long 0x00000000 /* var[13] */
.long 0x10000000 /* var[14] */
.long 0x20000000 /* var[15] */
.long 0x000005e4 /* var[16] */
.long 0x0000000e /* var[17] */
.long 0x000005e0 /* var[18] */
.long 0x00000004 /* var[19] */
.long 0x00000000 /* var[20] */
.long 0x00000000 /* var[21] */
.long 0x00000000 /* var[22] */
.long 0x00000000 /* var[23] */
.long 0x00000000 /* inc[0] */
.long 0x60000000 /* inc[1] */
.long 0x20000001 /* inc[2] */
.long 0x80000000 /* inc[3] */
.long 0x40000000 /* inc[4] */
.long 0x00000000 /* inc[5] */
.long 0x00000000 /* inc[6] */
.long 0x00000000 /* inc[7] */
.align 8
.globl scEthernetXmit_VarTab
scEthernetXmit_VarTab: /* Task 1 Variable Table */
.long 0x00000000 /* var[0] */
.long 0x00000000 /* var[1] */
.long 0x00000000 /* var[2] */
.long 0x00000000 /* var[3] */
.long 0x00000000 /* var[4] */
.long 0x00000000 /* var[5] */
.long 0x00000000 /* var[6] */
.long 0x00000000 /* var[7] */
.long 0x00000000 /* var[8] */
.long 0x00000000 /* var[9] */
.long 0x00000000 /* var[10] */
.long (CONFIG_SYS_MBAR + 0x8800) /* var[11] */
.long 0x00000000 /* var[12] */
.long 0x80000000 /* var[13] */
.long 0x10000000 /* var[14] */
.long 0x08000000 /* var[15] */
.long 0x20000000 /* var[16] */
.long 0x0000ffff /* var[17] */
.long 0xffffffff /* var[18] */
.long 0x00000008 /* var[19] */
.long 0x00000000 /* var[20] */
.long 0x00000000 /* var[21] */
.long 0x00000000 /* var[22] */
.long 0x00000000 /* var[23] */
.long 0x00000000 /* inc[0] */
.long 0x60000000 /* inc[1] */
.long 0x40000000 /* inc[2] */
.long 0x4000ffff /* inc[3] */
.long 0xe0000001 /* inc[4] */
.long 0x80000000 /* inc[5] */
.long 0x00000000 /* inc[6] */
.long 0x00000000 /* inc[7] */
.align 8
.globl scEthernetRecv_FDT
scEthernetRecv_FDT: /* Task 0 Function Descriptor Table */
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x21800000 /* and(), EU# 3 */
.long 0x21400000 /* andn(), EU# 3 */
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.align 8
.globl scEthernetXmit_FDT
scEthernetXmit_FDT: /* Task 1 Function Descriptor Table */
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x21800000 /* and(), EU# 3 */
.long 0x21400000 /* andn(), EU# 3 */
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.long 0x00000000
.globl scEthernetRecv_CSave
scEthernetRecv_CSave: /* Task 0 context save space */
.space 128, 0x0
.globl scEthernetXmit_CSave
scEthernetXmit_CSave: /* Task 1 context save space */
.space 128, 0x0

75
arch/powerpc/cpu/mpc5xxx/ide.c
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@ -1,75 +0,0 @@
/*
* (C) Copyright 2004
* Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Init is derived from Linux code.
*/
#include <common.h>
#if defined(CONFIG_IDE)
#include <mpc5xxx.h>
DECLARE_GLOBAL_DATA_PTR;
#define CALC_TIMING(t) (t + period - 1) / period
#ifdef CONFIG_IDE_RESET
extern void init_ide_reset (void);
#endif
int ide_preinit (void)
{
long period, t0, t1, t2_8, t2_16, t4, ta;
vu_long reg;
struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
/* ATA cs0/1 on i2c2 clk/io */
reg = (reg & ~0x03000000ul) | 0x02000000ul;
#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
/* ATA cs0/1 on Timer 0/1 */
reg = (reg & ~0x03000000ul) | 0x03000000ul;
#else
/* ATA cs0/1 on Local Plus cs4/5 */
reg = (reg & ~0x03000000ul) | 0x01000000ul;
#endif /* CONFIG_TOTAL5200 */
*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
/* All sample codes do that... */
*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
/* Configure and reset host */
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
udelay (10);
*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
/* Disable prefetch on Commbus */
psdma->PtdCntrl |= 1;
/* Init timings : we use PIO mode 0 timings */
period = 1000000000 / gd->arch.ipb_clk; /* period in ns */
t0 = CALC_TIMING (600);
t2_8 = CALC_TIMING (290);
t2_16 = CALC_TIMING (165);
reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
*(vu_long *) MPC5XXX_ATA_PIO1 = reg;
t4 = CALC_TIMING (30);
t1 = CALC_TIMING (70);
ta = CALC_TIMING (35);
reg = (t4 << 24) | (t1 << 16) | (ta << 8);
*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
#ifdef CONFIG_IDE_RESET
init_ide_reset ();
#endif /* CONFIG_IDE_RESET */
return (0);
}
#endif

330
arch/powerpc/cpu/mpc5xxx/interrupts.c
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@ -1,330 +0,0 @@
/*
* (C) Copyright 2006
* Detlev Zundel, DENX Software Engineering, dzu@denx.de
*
* (C) Copyright -2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
* Linux 2.6 source with the following copyright.
*
* Based on (well, mostly copied from) the code from the 2.4 kernel by
* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
*
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 Montavista Software, Inc
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
struct irq_action {
interrupt_handler_t *handler;
void *arg;
ulong count;
};
static struct irq_action irq_handlers[NR_IRQS];
static struct mpc5xxx_intr *intr;
static struct mpc5xxx_sdma *sdma;
static void mpc5xxx_ic_disable(unsigned int irq)
{
u32 val;
if (irq == MPC5XXX_IRQ0) {
val = in_be32(&intr->ctrl);
val &= ~(1 << 11);
out_be32(&intr->ctrl, val);
} else if (irq < MPC5XXX_IRQ1) {
BUG();
} else if (irq <= MPC5XXX_IRQ3) {
val = in_be32(&intr->ctrl);
val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
out_be32(&intr->ctrl, val);
} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
val = in_be32(&intr->main_mask);
val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
out_be32(&intr->main_mask, val);
} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
val = in_be32(&sdma->IntMask);
val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
out_be32(&sdma->IntMask, val);
} else {
val = in_be32(&intr->per_mask);
val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
out_be32(&intr->per_mask, val);
}
}
static void mpc5xxx_ic_enable(unsigned int irq)
{
u32 val;
if (irq == MPC5XXX_IRQ0) {
val = in_be32(&intr->ctrl);
val |= 1 << 11;
out_be32(&intr->ctrl, val);
} else if (irq < MPC5XXX_IRQ1) {
BUG();
} else if (irq <= MPC5XXX_IRQ3) {
val = in_be32(&intr->ctrl);
val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
out_be32(&intr->ctrl, val);
} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
val = in_be32(&intr->main_mask);
val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
out_be32(&intr->main_mask, val);
} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
val = in_be32(&sdma->IntMask);
val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
out_be32(&sdma->IntMask, val);
} else {
val = in_be32(&intr->per_mask);
val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
out_be32(&intr->per_mask, val);
}
}
static void mpc5xxx_ic_ack(unsigned int irq)
{
u32 val;
/*
* Only some irqs are reset here, others in interrupting hardware.
*/
switch (irq) {
case MPC5XXX_IRQ0:
val = in_be32(&intr->ctrl);
val |= 0x08000000;
out_be32(&intr->ctrl, val);
break;
case MPC5XXX_CCS_IRQ:
val = in_be32(&intr->enc_status);
val |= 0x00000400;
out_be32(&intr->enc_status, val);
break;
case MPC5XXX_IRQ1:
val = in_be32(&intr->ctrl);
val |= 0x04000000;
out_be32(&intr->ctrl, val);
break;
case MPC5XXX_IRQ2:
val = in_be32(&intr->ctrl);
val |= 0x02000000;
out_be32(&intr->ctrl, val);
break;
case MPC5XXX_IRQ3:
val = in_be32(&intr->ctrl);
val |= 0x01000000;
out_be32(&intr->ctrl, val);
break;
default:
if (irq >= MPC5XXX_SDMA_IRQ_BASE
&& irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
out_be32(&sdma->IntPend,
1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
}
break;
}
}
static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
{
mpc5xxx_ic_disable(irq);
mpc5xxx_ic_ack(irq);
}
static void mpc5xxx_ic_end(unsigned int irq)
{
mpc5xxx_ic_enable(irq);
}
void mpc5xxx_init_irq(void)
{
u32 intr_ctrl;
/* Remap the necessary zones */
intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
/* Disable all interrupt sources. */
out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
intr_ctrl = in_be32(&intr->ctrl);
intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
0x00ff0000 | /* IRQ 0-3 level sensitive low active */
0x00001000 | /* MEE master external enable */
0x00000000 | /* 0 means disable IRQ 0-3 */
0x00000001; /* CEb route critical normally */
out_be32(&intr->ctrl, intr_ctrl);
/* Zero a bunch of the priority settings. */
out_be32(&intr->per_pri1, 0);
out_be32(&intr->per_pri2, 0);
out_be32(&intr->per_pri3, 0);
out_be32(&intr->main_pri1, 0);
out_be32(&intr->main_pri2, 0);
}
int mpc5xxx_get_irq(struct pt_regs *regs)
{
u32 status;
int irq = -1;
status = in_be32(&intr->enc_status);
if (status & 0x00000400) { /* critical */
irq = (status >> 8) & 0x3;
if (irq == 2) /* high priority peripheral */
goto peripheral;
irq += MPC5XXX_CRIT_IRQ_BASE;
} else if (status & 0x00200000) { /* main */
irq = (status >> 16) & 0x1f;
if (irq == 4) /* low priority peripheral */
goto peripheral;
irq += MPC5XXX_MAIN_IRQ_BASE;
} else if (status & 0x20000000) { /* peripheral */
peripheral:
irq = (status >> 24) & 0x1f;
if (irq == 0) { /* bestcomm */
status = in_be32(&sdma->IntPend);
irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
} else
irq += MPC5XXX_PERP_IRQ_BASE;
}
return irq;
}
/****************************************************************************/
int interrupt_init_cpu(ulong * decrementer_count)
{
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
mpc5xxx_init_irq();
return (0);
}
/****************************************************************************/
/*
* Handle external interrupts
*/
void external_interrupt(struct pt_regs *regs)
{
int irq, unmask = 1;
irq = mpc5xxx_get_irq(regs);
mpc5xxx_ic_disable_and_ack(irq);
enable_interrupts();
if (irq_handlers[irq].handler != NULL)
(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
else {
printf("\nBogus External Interrupt IRQ %d\n", irq);
/*
* turn off the bogus interrupt, otherwise it
* might repeat forever
*/
unmask = 0;
}
if (unmask)
mpc5xxx_ic_end(irq);
}
void timer_interrupt_cpu(struct pt_regs *regs)
{
/* nothing to do here */
return;
}
/****************************************************************************/
/*
* Install and free a interrupt handler.
*/
void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
{
if (irq < 0 || irq >= NR_IRQS) {
printf("irq_install_handler: bad irq number %d\n", irq);
return;
}
if (irq_handlers[irq].handler != NULL)
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
(ulong) handler, (ulong) irq_handlers[irq].handler);
irq_handlers[irq].handler = handler;
irq_handlers[irq].arg = arg;
mpc5xxx_ic_enable(irq);
}
void irq_free_handler(int irq)
{
if (irq < 0 || irq >= NR_IRQS) {
printf("irq_free_handler: bad irq number %d\n", irq);
return;
}
mpc5xxx_ic_disable(irq);
irq_handlers[irq].handler = NULL;
irq_handlers[irq].arg = NULL;
}
/****************************************************************************/
#if defined(CONFIG_CMD_IRQ)
void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
int irq, re_enable;
u32 intr_ctrl;
char *irq_config[] = { "level sensitive, active high",
"edge sensitive, rising active edge",
"edge sensitive, falling active edge",
"level sensitive, active low"
};
re_enable = disable_interrupts();
intr_ctrl = in_be32(&intr->ctrl);
printf("Interrupt configuration:\n");
for (irq = 0; irq <= 3; irq++) {
printf("IRQ%d: %s\n", irq,
irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
}
puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
for (irq = 0; irq < NR_IRQS; irq++)
if (irq_handlers[irq].handler != NULL)
printf("%02d %08lx %08lx %ld\n", irq,
(ulong) irq_handlers[irq].handler,
(ulong) irq_handlers[irq].arg,
irq_handlers[irq].count);
if (re_enable)
enable_interrupts();
}
#endif

112
arch/powerpc/cpu/mpc5xxx/io.S
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@ -1,112 +0,0 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
* Copyright (C) 2003 Wolfgang Denk <wd@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <ppc_asm.tmpl>
/* ------------------------------------------------------------------------------- */
/* Function: in8 */
/* Description: Input 8 bits */
/* ------------------------------------------------------------------------------- */
.globl in8
in8:
lbz r3,0(r3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: in16 */
/* Description: Input 16 bits */
/* ------------------------------------------------------------------------------- */
.globl in16
in16:
lhz r3,0(r3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: in16r */
/* Description: Input 16 bits and byte reverse */
/* ------------------------------------------------------------------------------- */
.globl in16r
in16r:
lhbrx r3,0,r3
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: in32 */
/* Description: Input 32 bits */
/* ------------------------------------------------------------------------------- */
.globl in32
in32:
lwz 3,0(3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: in32r */
/* Description: Input 32 bits and byte reverse */
/* ------------------------------------------------------------------------------- */
.globl in32r
in32r:
lwbrx r3,0,r3
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: out8 */
/* Description: Output 8 bits */
/* ------------------------------------------------------------------------------- */
.globl out8
out8:
stb r4,0(r3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: out16 */
/* Description: Output 16 bits */
/* ------------------------------------------------------------------------------- */
.globl out16
out16:
sth r4,0(r3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: out16r */
/* Description: Byte reverse and output 16 bits */
/* ------------------------------------------------------------------------------- */
.globl out16r
out16r:
sthbrx r4,0,r3
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: out32 */
/* Description: Output 32 bits */
/* ------------------------------------------------------------------------------- */
.globl out32
out32:
stw r4,0(r3)
sync
blr
/* ------------------------------------------------------------------------------- */
/* Function: out32r */
/* Description: Byte reverse and output 32 bits */
/* ------------------------------------------------------------------------------- */
.globl out32r
out32r:
stwbrx r4,0,r3
sync
blr

76
arch/powerpc/cpu/mpc5xxx/loadtask.c
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@ -1,76 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on code
* (C) Copyright Motorola, Inc., 2000
*/
#include <common.h>
#include <mpc5xxx.h>
/* BestComm/SmartComm microcode */
extern int taskTable;
void loadtask(int basetask, int tasks)
{
int *sram = (int *)MPC5XXX_SRAM;
int *task_org = &taskTable;
unsigned int start, offset, end;
int i;
#ifdef DEBUG
printf("basetask = %d, tasks = %d\n", basetask, tasks);
printf("task_org = 0x%08x\n", (unsigned int)task_org);
#endif
/* setup TaskBAR register */
*(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM;
/* relocate task table entries */
offset = (unsigned int)sram;
for (i = basetask; i < basetask + tasks; i++) {
sram[i * 8 + 0] = task_org[i * 8 + 0] + offset;
sram[i * 8 + 1] = task_org[i * 8 + 1] + offset;
sram[i * 8 + 2] = task_org[i * 8 + 2] + offset;
sram[i * 8 + 3] = task_org[i * 8 + 3] + offset;
sram[i * 8 + 4] = task_org[i * 8 + 4];
sram[i * 8 + 5] = task_org[i * 8 + 5];
sram[i * 8 + 6] = task_org[i * 8 + 6] + offset;
sram[i * 8 + 7] = task_org[i * 8 + 7];
}
/* relocate task descriptors */
start = (sram[basetask * 8] - (unsigned int)sram);
end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram);
#ifdef DEBUG
printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end);
#endif
start /= 4;
end /= 4;
for (i = start; i <= end; i++) {
sram[i] = task_org[i];
}
/* relocate variables */
start = (sram[basetask * 8 + 2] - (unsigned int)sram);
end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram);
start /= 4;
end /= 4;
for (i = start; i < end; i++) {
sram[i] = task_org[i];
}
/* relocate function decriptors */
start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram);
end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram);
start /= 4;
end /= 4;
for (i = start; i < end; i++) {
sram[i] = task_org[i];
}
asm volatile ("sync");
}

157
arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
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@ -1,157 +0,0 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#if defined(CONFIG_PCI)
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <mpc5xxx.h>
/* System RAM mapped over PCI */
#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
/* PCIIWCR bit fields */
#define IWCR_MEM (0 << 3)
#define IWCR_IO (1 << 3)
#define IWCR_READ (0 << 1)
#define IWCR_READLINE (1 << 1)
#define IWCR_READMULT (2 << 1)
#define IWCR_EN (1 << 0)
static int mpc5200_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32* value)
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
udelay(10);
*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
udelay(10);
return 0;
}
static int mpc5200_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
eieio();
udelay(10);
out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
eieio();
*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
udelay(10);
return 0;
}
void pci_mpc5xxx_init (struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0xff;
/* System space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEMORY_BUS,
CONFIG_PCI_MEMORY_PHYS,
CONFIG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
pci_register_hose(hose);
/* GPIO Multiplexing - enable PCI */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
/* Set host bridge as pci master and enable memory decoding */
*(vu_long *)MPC5XXX_PCI_CMD |=
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
/* Set maximum latency timer */
*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
/* Set cache line size */
*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
(CONFIG_SYS_CACHELINE_SIZE / 4);
/* Map MBAR to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
*(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
/* Park XLB on PCI */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
/* Disable interrupts from PCI controller */
*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
/* Set PCI retry counter to 0 = infinite retry. */
/* The default of 255 is too short for slow devices. */
*(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
/* Disable initiator windows */
*(vu_long *)MPC5XXX_PCI_IWCR = 0;
/* Map PCI memory to physical space */
*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
(CONFIG_PCI_MEM_BUS >> 16);
*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
/* Map PCI I/O to physical space */
*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
(CONFIG_PCI_IO_BUS >> 16);
*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
/* Reset the PCI bus */
*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
udelay(1000);
*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
udelay(1000);
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
mpc5200_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
mpc5200_write_config_dword);
udelay(1000);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */

265
arch/powerpc/cpu/mpc5xxx/serial.c
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@ -1,265 +0,0 @@
/*
* (C) Copyright 2000 - 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
* changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*
* Martin Krause, 8 Jun 2006
* Added SERIAL_MULTI support
*/
/*
* Minimal serial functions needed to use one of the PSC ports
* as serial console interface.
*/
#include <common.h>
#include <linux/compiler.h>
#include <mpc5xxx.h>
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PSC_CONSOLE)
#if CONFIG_PSC_CONSOLE == 1
#define PSC_BASE MPC5XXX_PSC1
#elif CONFIG_PSC_CONSOLE == 2
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PSC_CONSOLE == 3
#define PSC_BASE MPC5XXX_PSC3
#elif CONFIG_PSC_CONSOLE == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PSC_CONSOLE == 5
#define PSC_BASE MPC5XXX_PSC5
#elif CONFIG_PSC_CONSOLE == 6
#define PSC_BASE MPC5XXX_PSC6
#else
#error CONFIG_PSC_CONSOLE must be in 1 ... 6
#endif
#if defined(CONFIG_PSC_CONSOLE2)
#if CONFIG_PSC_CONSOLE2 == 1
#define PSC_BASE2 MPC5XXX_PSC1
#elif CONFIG_PSC_CONSOLE2 == 2
#define PSC_BASE2 MPC5XXX_PSC2
#elif CONFIG_PSC_CONSOLE2 == 3
#define PSC_BASE2 MPC5XXX_PSC3
#elif CONFIG_PSC_CONSOLE2 == 4
#define PSC_BASE2 MPC5XXX_PSC4
#elif CONFIG_PSC_CONSOLE2 == 5
#define PSC_BASE2 MPC5XXX_PSC5
#elif CONFIG_PSC_CONSOLE2 == 6
#define PSC_BASE2 MPC5XXX_PSC6
#else
#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
#endif
#endif
int serial_init_dev (unsigned long dev_base)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
unsigned long baseclk;
int div;
/* reset PSC */
psc->command = PSC_SEL_MODE_REG_1;
/* select clock sources */
psc->psc_clock_select = 0;
baseclk = (gd->arch.ipb_clk + 16) / 32;
/* switch to UART mode */
psc->sicr = 0;
/* configure parity, bit length and so on */
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
psc->mode = PSC_MODE_ONE_STOP;
/* set up UART divisor */
div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xff;
psc->ctlr = div & 0xff;
/* disable all interrupts */
psc->psc_imr = 0;
/* reset and enable Rx/Tx */
psc->command = PSC_RST_RX;
psc->command = PSC_RST_TX;
psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
return (0);
}
void serial_putc_dev (unsigned long dev_base, const char c)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
if (c == '\n')
serial_putc_dev (dev_base, '\r');
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
;
psc->psc_buffer_8 = c;
}
void serial_puts_dev (unsigned long dev_base, const char *s)
{
while (*s) {
serial_putc_dev (dev_base, *s++);
}
}
int serial_getc_dev (unsigned long dev_base)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
/* Wait for a character to arrive. */
while (!(psc->psc_status & PSC_SR_RXRDY))
;
return psc->psc_buffer_8;
}
int serial_tstc_dev (unsigned long dev_base)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
return (psc->psc_status & PSC_SR_RXRDY);
}
void serial_setbrg_dev (unsigned long dev_base)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
unsigned long baseclk, div;
baseclk = (gd->arch.ipb_clk + 16) / 32;
/* set up UART divisor */
div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xFF;
psc->ctlr = div & 0xff;
}
void serial_setrts_dev (unsigned long dev_base, int s)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
if (s) {
/* Assert RTS (become LOW) */
psc->op1 = 0x1;
}
else {
/* Negate RTS (become HIGH) */
psc->op0 = 0x1;
}
}
int serial_getcts_dev (unsigned long dev_base)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
return (psc->ip & 0x1) ? 0 : 1;
}
int serial0_init(void)
{
return (serial_init_dev(PSC_BASE));
}
void serial0_setbrg (void)
{
serial_setbrg_dev(PSC_BASE);
}
void serial0_putc(const char c)
{
serial_putc_dev(PSC_BASE,c);
}
void serial0_puts(const char *s)
{
serial_puts_dev(PSC_BASE, s);
}
int serial0_getc(void)
{
return(serial_getc_dev(PSC_BASE));
}
int serial0_tstc(void)
{
return (serial_tstc_dev(PSC_BASE));
}
struct serial_device serial0_device =
{
.name = "serial0",
.start = serial0_init,
.stop = NULL,
.setbrg = serial0_setbrg,
.getc = serial0_getc,
.tstc = serial0_tstc,
.putc = serial0_putc,
.puts = serial0_puts,
};
__weak struct serial_device *default_serial_console(void)
{
return &serial0_device;
}
#ifdef CONFIG_PSC_CONSOLE2
int serial1_init(void)
{
return serial_init_dev(PSC_BASE2);
}
void serial1_setbrg(void)
{
serial_setbrg_dev(PSC_BASE2);
}
void serial1_putc(const char c)
{
serial_putc_dev(PSC_BASE2, c);
}
void serial1_puts(const char *s)
{
serial_puts_dev(PSC_BASE2, s);
}
int serial1_getc(void)
{
return serial_getc_dev(PSC_BASE2);
}
int serial1_tstc(void)
{
return serial_tstc_dev(PSC_BASE2);
}
struct serial_device serial1_device =
{
.name = "serial1",
.start = serial1_init,
.stop = NULL,
.setbrg = serial1_setbrg,
.getc = serial1_getc,
.tstc = serial1_tstc,
.putc = serial1_putc,
.puts = serial1_puts,
};
#endif /* CONFIG_PSC_CONSOLE2 */
#endif /* CONFIG_PSC_CONSOLE */

84
arch/powerpc/cpu/mpc5xxx/speed.c
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@ -1,84 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/* Bus-to-Core Multipliers */
static int bus2core[] = {
3, 2, 2, 2, 4, 4, 5, 9,
6, 11, 8, 10, 3, 12, 7, 0,
6, 5, 13, 2, 14, 4, 15, 9,
0, 11, 8, 10, 16, 12, 7, 0
};
/* ------------------------------------------------------------------------- */
/*
*
*/
int get_clocks (void)
{
ulong val, vco;
#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
#endif
val = *(vu_long *)MPC5XXX_CDM_PORCFG;
if (val & (1 << 6)) {
vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
} else {
vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
}
if (val & (1 << 5)) {
gd->bus_clk = vco / 8;
} else {
gd->bus_clk = vco / 4;
}
gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2;
val = *(vu_long *)MPC5XXX_CDM_CFG;
if (val & (1 << 8)) {
gd->arch.ipb_clk = gd->bus_clk / 2;
} else {
gd->arch.ipb_clk = gd->bus_clk;
}
switch (val & 3) {
case 0:
gd->pci_clk = gd->arch.ipb_clk;
break;
case 1:
gd->pci_clk = gd->arch.ipb_clk / 2;
break;
default:
gd->pci_clk = gd->bus_clk / 4;
break;
}
return (0);
}
int print_cpuinfo(void)
{
char buf1[32], buf2[32], buf3[32];
printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
strmhz(buf1, gd->bus_clk),
strmhz(buf2, gd->arch.ipb_clk),
strmhz(buf3, gd->pci_clk)
);
return (0);
}
/* ------------------------------------------------------------------------- */

76
arch/powerpc/cpu/mpc5xxx/spl_boot.c
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@ -1,76 +0,0 @@
/*
* Copyright (C) 2012 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Needed to align size SPL image to a 4-byte length
*/
u32 end_align __attribute__ ((section(".end_align")));
/*
* Return selected boot device. On MPC5200 its only NOR flash right now.
*/
u32 spl_boot_device(void)
{
return BOOT_DEVICE_NOR;
}
/*
* SPL version of board_init_f()
*/
void board_init_f(ulong bootflag)
{
end_align = (u32)__spl_flash_end;
/*
* On MPC5200, the initial RAM (and gd) is located in the internal
* SRAM. So we can actually call the preloader console init code
* before calling dram_init(). This makes serial output (printf)
* available very early, even before SDRAM init, which has been
* an U-Boot priciple from day 1.
*/
/*
* Init global_data pointer. Has to be done before calling
* get_clocks(), as it stores some clock values into gd needed
* later on in the serial driver.
*/
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
/*
* get_clocks() needs to be called so that the serial driver
* works correctly
*/
get_clocks();
/*
* Do rudimental console / serial setup
*/
preloader_console_init();
/*
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
/*
* Call board_init_r() (SPL framework version) to load and boot
* real U-Boot or OS
*/
board_init_r(NULL, 0);
/* Does not return!!! */
}

780
arch/powerpc/cpu/mpc5xxx/start.S
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@ -1,780 +0,0 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* U-Boot - Startup Code for MPC5xxx CPUs
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xxx.h>
#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>
/* We don't want the MMU yet.
*/
#undef MSR_KERNEL
/* Floating Point enable, Machine Check and Recoverable Interr. */
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Set up GOT: Global Offset Table
*
* Use r12 to access the GOT
*/
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
END_GOT
#endif
/*
* Version string
*/
.data
.globl version_string
version_string:
.ascii U_BOOT_VERSION_STRING, "\0"
/*
* Exception vectors
*/
.text
. = EXC_OFF_SYS_RESET
.globl _start
_start:
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
/*
* This is the entry of the real U-Boot from a board port
* that supports SPL booting on the MPC5200. We only need
* to call board_init_f() here. Everything else has already
* been done in the SPL u-boot version.
*/
GET_GOT /* initialize GOT access */
/*
* The GD (global data) struct needs to get cleared. Lets do
* this by calling memset().
* This function is called when the platform is build with SPL
* support from the main (full-blown) U-Boot. And the GD needs
* to get cleared (again) so that the following generic
* board support code initializes all variables correctly.
*/
mr r3, r2 /* parameter 1: GD pointer */
li r4,0 /* parameter 2: value to fill */
li r5,GD_SIZE /* parameter 3: count */
bl memset
li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#else
mfmsr r5 /* save msr contents */
/* Move CSBoot and adjust instruction pointer */
/*--------------------------------------------------------------*/
#if defined(CONFIG_SYS_LOWBOOT)
# if defined(CONFIG_SYS_RAMBOOT)
# error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
# endif /* CONFIG_SYS_RAMBOOT */
lis r4, CONFIG_SYS_DEFAULT_MBAR@h
lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4(r4) /* CS0 start */
lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x8(r4) /* CS0 stop */
lis r3, 0x02010000@h
ori r3, r3, 0x02010000@l
stw r3, 0x54(r4) /* CS0 and Boot enable */
lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
mtlr r3
blr
lowboot_reentry:
lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
stw r3, 0x4c(r4) /* Boot start */
lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
stw r3, 0x50(r4) /* Boot stop */
lis r3, 0x02000001@h
ori r3, r3, 0x02000001@l
stw r3, 0x54(r4) /* Boot enable, CS0 disable */
#endif /* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
lis r3, CONFIG_SYS_MBAR@h
ori r3, r3, CONFIG_SYS_MBAR@l
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
rlwinm r3, r3, 16, 16, 31
lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* Initialise the MPC5xxx processor core */
/*--------------------------------------------------------------*/
bl init_5xxx_core
/* initialize some things that are hard to access from C */
/*--------------------------------------------------------------*/
/* set up stack in on-chip SRAM */
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
/* let the C-code set up the rest */
/* */
/* Be careful to keep code relocatable ! */
/*--------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
GET_GOT /* initialize GOT access */
#endif
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Vector Table
*/
.globl _start_of_vectors
_start_of_vectors:
/* Machine check */
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x300, DataStorage, UnknownException)
/* Instruction Storage exception. */
STD_EXCEPTION(0x400, InstStorage, UnknownException)
/* External Interrupt exception. */
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
MSR_KERNEL, COPY_EE)
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
/* I guess we could implement decrementer, and may have
* to someday for timekeeping.
*/
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
#ifdef DEBUG
. = 0x1300
/*
* This exception occurs when the program counter matches the
* Instruction Address Breakpoint Register (IABR).
*
* I want the cpu to halt if this occurs so I can hunt around
* with the debugger and look at things.
*
* When DEBUG is defined, both machine check enable (in the MSR)
* and checkstop reset enable (in the reset mode register) are
* turned off and so a checkstop condition will result in the cpu
* halting.
*
* I force the cpu into a checkstop condition by putting an illegal
* instruction here (at least this is the theory).
*
* well - that didnt work, so just do an infinite loop!
*/
1: b 1b
#else
STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
#endif
STD_EXCEPTION(0x1400, SMI, UnknownException)
STD_EXCEPTION(0x1500, Trap_15, UnknownException)
STD_EXCEPTION(0x1600, Trap_16, UnknownException)
STD_EXCEPTION(0x1700, Trap_17, UnknownException)
STD_EXCEPTION(0x1800, Trap_18, UnknownException)
STD_EXCEPTION(0x1900, Trap_19, UnknownException)
STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
STD_EXCEPTION(0x2000, Trap_20, UnknownException)
STD_EXCEPTION(0x2100, Trap_21, UnknownException)
STD_EXCEPTION(0x2200, Trap_22, UnknownException)
STD_EXCEPTION(0x2300, Trap_23, UnknownException)
STD_EXCEPTION(0x2400, Trap_24, UnknownException)
STD_EXCEPTION(0x2500, Trap_25, UnknownException)
STD_EXCEPTION(0x2600, Trap_26, UnknownException)
STD_EXCEPTION(0x2700, Trap_27, UnknownException)
STD_EXCEPTION(0x2800, Trap_28, UnknownException)
STD_EXCEPTION(0x2900, Trap_29, UnknownException)
STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
.globl _end_of_vectors
_end_of_vectors:
. = 0x3000
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
* Register r21 is pointer into trap frame, r1 has new stack pointer.
*/
.globl transfer_to_handler
transfer_to_handler:
stw r22,_NIP(r21)
lis r22,MSR_POW@h
andc r23,r23,r22
stw r23,_MSR(r21)
SAVE_GPR(7, r21)
SAVE_4GPRS(8, r21)
SAVE_8GPRS(12, r21)
SAVE_8GPRS(24, r21)
mflr r23
andi. r24,r23,0x3f00 /* get vector offset */
stw r24,TRAP(r21)
li r22,0
stw r22,RESULT(r21)
lwz r24,0(r23) /* virtual address of handler */
lwz r23,4(r23) /* where to go when done */
mtspr SRR0,r24
mtspr SRR1,r20
mtlr r23
SYNC
rfi /* jump to handler, enable MMU */
int_return:
mfmsr r28 /* Disable interrupts */
li r4,0
ori r4,r4,MSR_EE
andc r28,r28,r4
SYNC /* Some chip revs need this... */
mtmsr r28
SYNC
lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
lwz r2,_XER(r1)
lwz r0,_CCR(r1)
mtspr XER,r2
mtcrf 0xFF,r0
REST_10GPRS(3, r1)
REST_10GPRS(13, r1)
REST_8GPRS(23, r1)
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
mtspr SRR0,r2
mtspr SRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfi
#endif /* CONFIG_SPL_BUILD */
/*
* This code initialises the MPC5xxx processor core
* (conforms to PowerPC 603e spec)
* Note: expects original MSR contents to be in r5.
*/
.globl init_5xx_core
init_5xxx_core:
/* Initialize machine status; enable machine check interrupt */
/*--------------------------------------------------------------*/
li r3, MSR_KERNEL /* Set ME and RI flags */
rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
#ifdef DEBUG
rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
#endif
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtspr SRR1, r3 /* Make SRR1 match MSR */
/* Initialize the Hardware Implementation-dependent Registers */
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
lis r3, CONFIG_SYS_HID0_INIT@h
ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
lis r3, CONFIG_SYS_HID0_FINAL@h
ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
/* clear all BAT's */
/*--------------------------------------------------------------*/
li r0, 0
mtspr DBAT0U, r0
mtspr DBAT0L, r0
mtspr DBAT1U, r0
mtspr DBAT1L, r0
mtspr DBAT2U, r0
mtspr DBAT2L, r0
mtspr DBAT3U, r0
mtspr DBAT3L, r0
mtspr DBAT4U, r0
mtspr DBAT4L, r0
mtspr DBAT5U, r0
mtspr DBAT5L, r0
mtspr DBAT6U, r0
mtspr DBAT6L, r0
mtspr DBAT7U, r0
mtspr DBAT7L, r0
mtspr IBAT0U, r0
mtspr IBAT0L, r0
mtspr IBAT1U, r0
mtspr IBAT1L, r0
mtspr IBAT2U, r0
mtspr IBAT2L, r0
mtspr IBAT3U, r0
mtspr IBAT3L, r0
mtspr IBAT4U, r0
mtspr IBAT4L, r0
mtspr IBAT5U, r0
mtspr IBAT5L, r0
mtspr IBAT6U, r0
mtspr IBAT6L, r0
mtspr IBAT7U, r0
mtspr IBAT7L, r0
SYNC
/* invalidate all tlb's */
/* */
/* From the 603e User Manual: "The 603e provides the ability to */
/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
/* instruction invalidates the TLB entry indexed by the EA, and */
/* operates on both the instruction and data TLBs simultaneously*/
/* invalidating four TLB entries (both sets in each TLB). The */
/* index corresponds to bits 15-19 of the EA. To invalidate all */
/* entries within both TLBs, 32 tlbie instructions should be */
/* issued, incrementing this field by one each time." */
/* */
/* "Note that the tlbia instruction is not implemented on the */
/* 603e." */
/* */
/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
/* incrementing by 0x1000 each time. The code below is sort of */
/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
/* */
/*--------------------------------------------------------------*/
li r3, 32
mtctr r3
li r3, 0
1: tlbie r3
addi r3, r3, 0x1000
bdnz 1b
SYNC
/* Done! */
/*--------------------------------------------------------------*/
blr
/* Cache functions.
*
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
.globl icache_enable
icache_enable:
mfspr r3, HID0
ori r3, r3, HID0_ICE
lis r4, 0
ori r4, r4, HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_disable
icache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_ICE|HID0_ILOCK
andc r3, r3, r4
ori r4, r3, HID0_ICFI
isync
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
isync
mtspr HID0, r3 /* clears invalidate */
blr
.globl icache_status
icache_status:
mfspr r3, HID0
rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
blr
.globl dcache_enable
dcache_enable:
mfspr r3, HID0
ori r3, r3, HID0_DCE
lis r4, 0
ori r4, r4, HID0_DLOCK
andc r3, r3, r4
ori r4, r3, HID0_DCI
sync
mtspr HID0, r4 /* sets enable and invalidate, clears lock */
sync
mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_disable
dcache_disable:
mfspr r3, HID0
lis r4, 0
ori r4, r4, HID0_DCE|HID0_DLOCK
andc r3, r3, r4
ori r4, r3, HID0_DCI
sync
mtspr HID0, r4 /* sets invalidate, clears enable and lock */
sync
mtspr HID0, r3 /* clears invalidate */
blr
.globl dcache_status
dcache_status:
mfspr r3, HID0
rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
blr
.globl get_svr
get_svr:
mfspr r3, SVR
blr
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
#ifndef CONFIG_SPL_BUILD
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
* r3 = dest
* r4 = src
* r5 = length in bytes
* r6 = cachelinesize
*/
.globl relocate_code
relocate_code:
mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Global Data pointer */
mr r10, r5 /* Save copy of Destination Address */
GET_GOT
mr r3, r5 /* Destination Address */
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
sub r15, r10, r4
/* First our own GOT */
add r12, r12, r15
/* then the one used by the C code */
add r30, r30, r15
/*
* Now relocate code
*/
cmplw cr1,r3,r4
addi r0,r5,3
srwi. r0,r0,2
beq cr1,4f /* In place copy is not necessary */
beq 7f /* Protect against 0 count */
mtctr r0
bge cr1,2f
la r8,-4(r4)
la r7,-4(r3)
1: lwzu r0,4(r8)
stwu r0,4(r7)
bdnz 1b
b 4f
2: slwi r0,r0,2
add r8,r4,r0
add r7,r3,r0
3: lwzu r0,-4(r8)
stwu r0,-4(r7)
bdnz 3b
/*
* Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line.
*/
4: cmpwi r6,0
add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */
subi r0,r6,1
andc r3,r3,r0
mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
cmpwi r7,0
beq 9f
mr r4,r3
5: dcbst 0,r4
add r4,r4,r6
cmplw r4,r5
blt 5b
sync /* Wait for all dcbst to complete on bus */
9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
cmpwi r7,0
beq 7f
mr r4,r3
6: icbi 0,r4
add r4,r4,r6
cmplw r4,r5
blt 6b
7: sync /* Wait for all icbi to complete on bus */
isync
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
mtlr r0
blr
in_ram:
/*
* Relocation Function, r12 point to got2+0x8000
*
* Adjust got2 pointers, no need to check for 0, this code
* already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr r0
sub r11,r3,r11
addi r3,r3,-4
1: lwzu r0,4(r3)
cmpwi r0,0
beq- 2f
add r0,r0,r11
stw r0,0(r3)
2: bdnz 1b
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
li r0,__fixup_entries@sectoff@l
lwz r3,GOT(_FIXUP_TABLE_)
cmpwi r0,0
mtctr r0
addi r3,r3,-4
beq 4f
3: lwzu r4,4(r3)
lwzux r0,r4,r11
cmpwi r0,0
add r0,r0,r11
stw r4,0(r3)
beq- 5f
stw r0,0(r4)
5: bdnz 3b
4:
clear_bss:
/*
* Now clear BSS segment
*/
lwz r3,GOT(__bss_start)
lwz r4,GOT(__bss_end)
cmplw 0, r3, r4
beq 6f
li r0, 0
5:
stw r0, 0(r3)
addi r3, r3, 4
cmplw 0, r3, r4
bne 5b
6:
mr r3, r9 /* Global Data pointer */
mr r4, r10 /* Destination Address */
bl board_init_r
/*
* Copy exception vector code to low memory
*
* r3: dest_addr
* r7: source address, r8: end address, r9: target address
*/
.globl trap_init
trap_init:
mflr r4 /* save link register */
GET_GOT
lwz r7, GOT(_start)
lwz r8, GOT(_end_of_vectors)
li r9, 0x100 /* reset vector always at 0x100 */
cmplw 0, r7, r8
bgelr /* return if r7>=r8 - just in case */
1:
lwz r0, 0(r7)
stw r0, 0(r9)
addi r7, r7, 4
addi r9, r9, 4
cmplw 0, r7, r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
li r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 2b
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
bl trap_reloc
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 3b
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
bl trap_reloc
addi r7, r7, 0x100 /* next exception vector */
cmplw 0, r7, r8
blt 4b
mfmsr r3 /* now that the vectors have */
lis r7, MSR_IP@h /* relocated into low memory */
ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
andc r3, r3, r7 /* (if it was on) */
SYNC /* Some chip revs need this... */
mtmsr r3
SYNC
mtlr r4 /* restore link register */
blr
#endif /* CONFIG_SPL_BUILD */

220
arch/powerpc/cpu/mpc5xxx/traps.c
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@ -1,220 +0,0 @@
/*
* linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Modified by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras (paulus@cs.anu.edu.au)
* fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de)
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* This file handles the architecture-dependent parts of hardware exceptions
*/
#include <common.h>
#include <command.h>
#include <kgdb.h>
#include <asm/processor.h>
/* Returns 0 if exception not found and fixup otherwise. */
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
*/
#define END_OF_MEM 0x02000000
/*
* Trap & Exception support
*/
static void print_backtrace(unsigned long *sp)
{
int cnt = 0;
unsigned long i;
printf("Call backtrace: ");
while (sp) {
if ((uint)sp > END_OF_MEM)
break;
i = sp[1];
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
if (cnt > 32) break;
sp = (unsigned long *)*sp;
}
printf("\n");
}
void show_regs(struct pt_regs *regs)
{
int i;
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
regs->msr&MSR_IR ? 1 : 0,
regs->msr&MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
{
printf("GPR%02d: ", i);
}
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
{
printf("\n");
}
}
}
static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
}
void MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
if ((fixup = search_exception_table(regs->nip)) != 0) {
regs->nip = fixup;
return;
}
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
printf("regs %p ",regs);
/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
switch( regs->msr & 0x000F0000)
{
case (0x80000000>>12) :
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
case (0x80000000>>13) :
printf("Transfer error ack signal\n");
break;
case (0x80000000>>14) :
printf("Data parity signal\n");
break;
case (0x80000000>>15) :
printf("Address parity signal\n");
break;
default:
printf("Unknown values in msr\n");
}
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");
}
void AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Alignment Exception");
}
void ProgramCheckException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
}
void SoftEmuException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Software Emulation Exception");
}
void UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif
void DebugException(struct pt_regs *regs)
{
printf("Debugger trap at @ %lx\n", regs->nip );
show_regs(regs);
#if defined(CONFIG_CMD_BEDBUG)
do_bedbug_breakpoint( regs );
#endif
}
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
int addr_probe(uint *addr)
{
#if 0
int retval;
__asm__ __volatile__( \
"1: lwz %0,0(%1)\n" \
" eieio\n" \
" li %0,0\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3: li %0,-1\n" \
" b 2b\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,3b\n" \
".text" \
: "=r" (retval) : "r"(addr));
return (retval);
#endif
return 0;
}

80
arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
View File

@ -1,80 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc5xxx/start.o (.text*)
arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
*(.text*)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

44
arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
View File

@ -1,44 +0,0 @@
/*
* Copyright 2012 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY
{
sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
LENGTH = CONFIG_SPL_BSS_MAX_SIZE
flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
LENGTH = CONFIG_SYS_SPL_MAX_LEN
}
OUTPUT_ARCH(powerpc)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
arch/powerpc/cpu/mpc5xxx/start.o (.text)
*(.text*)
} > flash
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
. = ALIGN(4);
.end_align : { *(.end_align*) } > flash
__spl_flash_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > sdram
}

75
arch/powerpc/cpu/mpc5xxx/u-boot.lds
View File

@ -1,75 +0,0 @@
/*
* (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text :
{
arch/powerpc/cpu/mpc5xxx/start.o (.text*)
arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
*(.text*)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(COMMON)
*(.bss*)
*(.sbss*)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

42
arch/powerpc/cpu/mpc5xxx/usb.c
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@ -1,42 +0,0 @@
/*
* (C) Copyright 2007
* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <mpc5xxx.h>
int usb_cpu_init(void)
{
/* Set the USB Clock */
*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
/* remove all PSC3 USB bits first before ORing in ours */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
#else
/* remove all USB bits first before ORing in ours */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
#endif
/* Activate USB port */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
return 0;
}
int usb_cpu_stop(void)
{
return 0;
}
int usb_cpu_init_fail(void)
{
return 0;
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

1529
arch/powerpc/cpu/mpc5xxx/usb_ohci.c
View File

File diff suppressed because it is too large Load Diff

418
arch/powerpc/cpu/mpc5xxx/usb_ohci.h
View File

@ -1,418 +0,0 @@
/*
* URB OHCI HCD (Host Controller Driver) for USB.
*
* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
*
* usb-ohci.h
*/
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
};
/* ED States */
#define ED_NEW 0x00
#define ED_UNLINK 0x01
#define ED_OPER 0x02
#define ED_DEL 0x04
#define ED_URB_DEL 0x08
/* usb_ohci_ed */
struct ed {
__u32 hwINFO;
__u32 hwTailP;
__u32 hwHeadP;
__u32 hwNextED;
struct ed *ed_prev;
__u8 int_period;
__u8 int_branch;
__u8 int_load;
__u8 int_interval;
__u8 state;
__u8 type;
__u16 last_iso;
struct ed *ed_rm_list;
struct usb_device *usb_dev;
__u32 unused[3];
} __attribute__((aligned(16)));
typedef struct ed ed_t;
/* TD info field */
#define TD_CC 0xf0000000
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
#define TD_T_DATA1 0x03000000
#define TD_T_TOGGLE 0x00000000
#define TD_R 0x00040000
#define TD_DI 0x00E00000
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
#define TD_DP 0x00180000
#define TD_DP_SETUP 0x00000000
#define TD_DP_IN 0x00100000
#define TD_DP_OUT 0x00080000
#define TD_ISO 0x00010000
#define TD_DEL 0x00020000
/* CC Codes */
#define TD_CC_NOERROR 0x00
#define TD_CC_CRC 0x01
#define TD_CC_BITSTUFFING 0x02
#define TD_CC_DATATOGGLEM 0x03
#define TD_CC_STALL 0x04
#define TD_DEVNOTRESP 0x05
#define TD_PIDCHECKFAIL 0x06
#define TD_UNEXPECTEDPID 0x07
#define TD_DATAOVERRUN 0x08
#define TD_DATAUNDERRUN 0x09
#define TD_BUFFEROVERRUN 0x0C
#define TD_BUFFERUNDERRUN 0x0D
#define TD_NOTACCESSED 0x0F
#define MAXPSW 1
struct td {
__u32 hwINFO;
__u32 hwCBP; /* Current Buffer Pointer */
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
__u8 unused;
__u8 index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
__u32 data;
__u32 unused2[2];
} __attribute__((aligned(32)));
typedef struct td td_t;
#define OHCI_ED_SKIP (1 << 14)
/*
* The HCCA (Host Controller Communications Area) is a 256 byte
* structure defined in the OHCI spec. that the host controller is
* told the base address of. It must be 256-byte aligned.
*/
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
__u16 pad1; /* set to 0 on each frame_no change */
__u16 frame_no; /* current frame number */
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute__((aligned(256)));
/*
* Maximum number of root hub ports.
*/
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
/*
* This is the structure of the OHCI controller's memory mapped I/O
* region. This is Memory Mapped I/O. You must use the readl() and
* writel() macros defined in asm/io.h to access these!!
*/
struct ohci_regs {
/* control and status registers */
__u32 revision;
__u32 control;
__u32 cmdstatus;
__u32 intrstatus;
__u32 intrenable;
__u32 intrdisable;
/* memory pointers */
__u32 hcca;
__u32 ed_periodcurrent;
__u32 ed_controlhead;
__u32 ed_controlcurrent;
__u32 ed_bulkhead;
__u32 ed_bulkcurrent;
__u32 donehead;
/* frame counters */
__u32 fminterval;
__u32 fmremaining;
__u32 fmnumber;
__u32 periodicstart;
__u32 lsthresh;
/* Root hub ports */
struct ohci_roothub_regs {
__u32 a;
__u32 b;
__u32 status;
__u32 portstatus[MAX_ROOT_PORTS];
} roothub;
} __attribute__((aligned(32)));
/* OHCI CONTROL AND STATUS REGISTER MASKS */
/*
* HcControl (control) register masks
*/
#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
/* pre-shifted values for HCFS */
# define OHCI_USB_RESET (0 << 6)
# define OHCI_USB_RESUME (1 << 6)
# define OHCI_USB_OPER (2 << 6)
# define OHCI_USB_SUSPEND (3 << 6)
/*
* HcCommandStatus (cmdstatus) register masks
*/
#define OHCI_HCR (1 << 0) /* host controller reset */
#define OHCI_CLF (1 << 1) /* control list filled */
#define OHCI_BLF (1 << 2) /* bulk list filled */
#define OHCI_OCR (1 << 3) /* ownership change request */
#define OHCI_SOC (3 << 16) /* scheduling overrun count */
/*
* masks used with interrupt registers:
* HcInterruptStatus (intrstatus)
* HcInterruptEnable (intrenable)
* HcInterruptDisable (intrdisable)
*/
#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
#define OHCI_INTR_SF (1 << 2) /* start frame */
#define OHCI_INTR_RD (1 << 3) /* resume detect */
#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
#define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
};
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
/* destination of request */
#define RH_INTERFACE 0x01
#define RH_ENDPOINT 0x02
#define RH_OTHER 0x03
#define RH_CLASS 0x20
#define RH_VENDOR 0x40
/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS 0x0080
#define RH_CLEAR_FEATURE 0x0100
#define RH_SET_FEATURE 0x0300
#define RH_SET_ADDRESS 0x0500
#define RH_GET_DESCRIPTOR 0x0680
#define RH_SET_DESCRIPTOR 0x0700
#define RH_GET_CONFIGURATION 0x0880
#define RH_SET_CONFIGURATION 0x0900
#define RH_GET_STATE 0x0280
#define RH_GET_INTERFACE 0x0A80
#define RH_SET_INTERFACE 0x0B00
#define RH_SYNC_FRAME 0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP 0x2000
/* Hub port features */
#define RH_PORT_CONNECTION 0x00
#define RH_PORT_ENABLE 0x01
#define RH_PORT_SUSPEND 0x02
#define RH_PORT_OVER_CURRENT 0x03
#define RH_PORT_RESET 0x04
#define RH_PORT_POWER 0x08
#define RH_PORT_LOW_SPEED 0x09
#define RH_C_PORT_CONNECTION 0x10
#define RH_C_PORT_ENABLE 0x11
#define RH_C_PORT_SUSPEND 0x12
#define RH_C_PORT_OVER_CURRENT 0x13
#define RH_C_PORT_RESET 0x14
/* Hub features */
#define RH_C_HUB_LOCAL_POWER 0x00
#define RH_C_HUB_OVER_CURRENT 0x01
#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL 0x01
#define RH_ACK 0x01
#define RH_REQ_ERR -1
#define RH_NACK 0x00
/* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */
#define RH_PS_CCS 0x00000001 /* current connect status */
#define RH_PS_PES 0x00000002 /* port enable status*/
#define RH_PS_PSS 0x00000004 /* port suspend status */
#define RH_PS_POCI 0x00000008 /* port over current indicator */
#define RH_PS_PRS 0x00000010 /* port reset status */
#define RH_PS_PPS 0x00000100 /* port power status */
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
#define RH_PS_CSC 0x00010000 /* connect status change */
#define RH_PS_PESC 0x00020000 /* port enable status change */
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
#define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */
#define RH_HS_LPS 0x00000001 /* local power status */
#define RH_HS_OCI 0x00000002 /* over current indicator */
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
#define RH_HS_LPSC 0x00010000 /* local power status change */
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */
#define RH_B_DR 0x0000ffff /* device removable flags */
#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
#define RH_A_PSM (1 << 8) /* power switching mode */
#define RH_A_NPS (1 << 9) /* no power switching */
#define RH_A_DT (1 << 10) /* device type (mbz) */
#define RH_A_OCPM (1 << 11) /* over current protection mode */
#define RH_A_NOCP (1 << 12) /* no over current protection */
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
/* urb */
#define N_URB_TD 48
typedef struct
{
ed_t *ed;
__u16 length; /* number of tds associated with this request */
__u16 td_cnt; /* number of tds already serviced */
int state;
unsigned long pipe;
int actual_length;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
} urb_priv_t;
#define URB_DEL 1
/*
* This is the full ohci controller description
*
* Note how the "proper" USB information is just
* a subset of what the full implementation needs. (Linus)
*/
typedef struct ohci {
struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma;*/
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
unsigned long flags; /* for HC bugs */
struct ohci_regs *regs; /* OHCI controller's memory */
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_device *dev[32];
struct virt_root_hub rh;
const char *slot_name;
} ohci_t;
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device {
ed_t ed[NUM_EDS];
int ed_cnt;
};
/* hcd */
/* endpoint */
static int ep_link(ohci_t * ohci, ed_t * ed);
static int ep_unlink(ohci_t * ohci, ed_t * ed);
static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
/*-------------------------------------------------------------------------*/
/* we need more TDs than EDs */
#define NUM_TD 64
/* +1 so we can align the storage */
td_t gtd[NUM_TD+1];
/* pointers to aligned storage */
td_t *ptd;
/* TDs ... */
static inline struct td *
td_alloc (struct usb_device *usb_dev)
{
int i;
struct td *td;
td = NULL;
for (i = 0; i < NUM_TD; i++)
{
if (ptd[i].usb_dev == NULL)
{
td = &ptd[i];
td->usb_dev = usb_dev;
break;
}
}
return td;
}
static inline void
ed_free (struct ed *ed)
{
ed->usb_dev = NULL;
}

3
arch/powerpc/cpu/ppc4xx/usb_ohci.c
View File

@ -782,9 +782,6 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
} else
td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
}
#ifdef CONFIG_MPC5200
td_list->hwNextTD = 0;
#endif
}
td_list->next_dl_td = td_rev;

5
arch/powerpc/cpu/ppc4xx/usb_ohci.h
View File

@ -125,13 +125,8 @@ typedef struct td td_t;
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
#if defined(CONFIG_MPC5200)
__u16 pad1; /* set to 0 on each frame_no change */
__u16 frame_no; /* current frame number */
#else
__u16 frame_no; /* current frame number */
__u16 pad1; /* set to 0 on each frame_no change */
#endif
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute__((aligned(256)));

7
arch/powerpc/include/asm/global_data.h
View File

@ -81,13 +81,6 @@ struct arch_global_data {
#if defined(CONFIG_E500)
u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
#endif
#if defined(CONFIG_MPC512X)
u32 ips_clk;
u32 csb_clk;
#endif /* CONFIG_MPC512X */
unsigned long reset_status; /* reset status register at boot */
#if defined(CONFIG_MPC83xx)
unsigned long arbiter_event_attributes;

1264
arch/powerpc/include/asm/immap_512x.h
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File diff suppressed because it is too large Load Diff

42
arch/powerpc/include/asm/mpc512x.h
View File

@ -1,42 +0,0 @@
/*
* include/asm-ppc/mpc512x.h
*
* Prototypes, etc. for the Freescale MPC512x embedded cpu chips
*
* 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASMPPC_MPC512X_H
#define __ASMPPC_MPC512X_H
/*
* macros for manipulating CSx_START/STOP
*/
#define CSAW_START(start) ((start) & 0xFFFF0000)
#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
/*
* Inlines
*/
/*
* According to MPC5121e RM, configuring local access windows should
* be followed by a dummy read of the config register that was
* modified last and an isync.
*/
static inline void sync_law(volatile void *addr)
{
in_be32(addr);
__asm__ __volatile__ ("isync");
}
/*
* Prototypes
*/
extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
u32 *dram_init_seq, int seq_sz);
extern int mpc5121_diu_init(void);
extern void ide_set_reset(int idereset);
#endif /* __ASMPPC_MPC512X_H */

13
arch/powerpc/include/asm/ppc.h
View File

@ -13,11 +13,6 @@
#ifndef __ASSEMBLY__
#if defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
#include <asm/immap_86xx.h>
@ -43,9 +38,6 @@
#include <asm/arch/immap_lsch2.h>
#endif
#if defined(CONFIG_MPC5xxx)
uint get_svr(void);
#endif
uint get_pvr(void);
uint get_svr(void);
uint rd_ic_cst(void);
@ -56,7 +48,6 @@ void wr_dc_cst(uint);
void wr_dc_adr(uint);
#if defined(CONFIG_4xx) || \
defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
@ -85,10 +76,6 @@ void ddr_enable_ecc(unsigned int dram_size);
#endif
#endif
#if defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks(void);
#endif
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info(sys_info_t *);

18
arch/powerpc/lib/Makefile
View File

@ -37,24 +37,6 @@ obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
obj-y += stack.o
obj-y += time.o
# Don't include the MPC5xxx special memcpy into the
# SPL U-Boot image. memcpy is used in the SPL NOR
# flash driver. And we need the real, fast memcpy
# here. We have no problems with unaligned access.
ifndef CONFIG_SPL_BUILD
# Workaround for local bus unaligned access problems
# on MPC512x and MPC5200
ifdef CONFIG_MPC512X
AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
obj-y += memcpy_mpc5200.o
endif
ifdef CONFIG_MPC5200
AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
obj-y += memcpy_mpc5200.o
endif
endif
endif # not minimal
ifdef CONFIG_SPL_BUILD

4
arch/powerpc/lib/bootm.c
View File

@ -283,10 +283,6 @@ static void set_clocks_in_mhz (bd_t *kbd)
kbd->bi_sccfreq /= 1000000L;
kbd->bi_vco /= 1000000L;
#endif
#if defined(CONFIG_MPC5xxx)
kbd->bi_ipbfreq /= 1000000L;
kbd->bi_pcifreq /= 1000000L;
#endif /* CONFIG_MPC5xxx */
}
}

55
arch/powerpc/lib/memcpy_mpc5200.c
View File

@ -1,55 +0,0 @@
/*
* (C) Copyright 2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* This is a workaround for issues on the MPC5200, where unaligned
* 32-bit-accesses to the local bus will deliver corrupted data. This
* happens for example when trying to use memcpy() from an odd NOR
* flash address; the behaviour can be also seen when using "md" on an
* odd NOR flash address (but there it is not a bug in U-Boot, which
* only shows the behaviour of this processor).
*
* For memcpy(), we test if either the source or the target address
* are not 32 bit aligned, and - if so - if the source address is in
* NOR flash: in this case we perform a byte-wise (slow) then; for
* aligned operations of non-flash areas we use the optimized (fast)
* real __memcpy(). This way we minimize the performance impact of
* this workaround.
*
*/
#include <common.h>
#include <flash.h>
#include <linux/types.h>
void *memcpy(void *trg, const void *src, size_t len)
{
extern void* __memcpy(void *, const void *, size_t);
char *s = (char *)src;
char *t = (char *)trg;
void *dest = (void *)trg;
/*
* Check is source address is in flash:
* If not, we use the fast assembler code
*/
if (((((unsigned long)s & 3) == 0) /* source aligned */
&& /* AND */
(((unsigned long)t & 3) == 0)) /* target aligned, */
|| /* or */
(addr2info((ulong)s) == NULL)) { /* source not in flash */
return __memcpy(trg, src, len);
}
/*
* Copying from flash, perform byte by byte copy.
*/
while (len-- > 0)
*t++ = *s++;
return dest;
}

9
board/a3m071/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_A3M071
config SYS_BOARD
default "a3m071"
config SYS_CONFIG_NAME
default "a3m071"
endif

7
board/a3m071/MAINTAINERS
View File

@ -1,7 +0,0 @@
A3M071 BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/a3m071/
F: include/configs/a3m071.h
F: configs/a3m071_defconfig
F: configs/a4m2k_defconfig

5
board/a3m071/Makefile
View File

@ -1,5 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := a3m071.o

80
board/a3m071/README
View File

@ -1,80 +0,0 @@
------------------------------------------------------------------------
A3M071 board support
------------------------------------------------------------------------
SPL NOR flash support:
----------------------
To boot fast into the OS (Linux), this board port integrates the SPL
framework. This means, that a special, stripped-down version of
U-Boot runs in the beginning. In the case of the A3M071 board, this
SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
boot the OS (Linux) or a "real", full-blown U-Boot. This detection
on whether to boot Linux or U-Boot is done by using the "boot_os"
environment variable. If "boot_os" is set to "yes", Linux will be
loaded and booted from the SPL U-Boot version. Otherwise, the
full-blown U-Boot version will be loaded and run.
Enabling Linux booting:
-----------------------
From U-Boot:
=> setenv boot_os yes
=> saveenv
From Linux:
$ fw_setenv boot_os yes
Enabling U-Boot booting:
------------------------
From U-Boot:
=> setenv boot_os no
=> saveenv
From Linux:
$ fw_setenv boot_os no
Preparing Linux image(s) for booting from SPL U-Boot:
-----------------------------------------------------
To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
prepard/patched first. U-Boot usually inserts some dynamic values into
the DT binary (blob), e.g. autodetected memory size, MAC addresses,
clocks speeds etc. To generate this patched DT blob, you can use
the following command:
1. Load fdt blob to SDRAM:
=> tftp 1800000 a3m071/a3m071.dtb
2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
=> run mtdargs addip2 addtty
3. Use "fdt" commands to patch the DT blob:
=> fdt addr 1800000
=> fdt boardsetup
=> fdt chosen
4. Display patched DT blob (optional):
=> fdt print
5. Save fdt to NOR flash:
=> erase fc180000 fc07ffff
=> cp.b 1800000 fc180000 10000
All this can be integrated into an environment command:
=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
cp.b 1800000 fc180000 10000'
=> saveenv
After this, only "run upd_fdt" needs to get called to load, patch
and save the DT blob into NOR flash.
Additionally, the Linux kernel image has to be saved uncompressed in
its uImage file (and not gzip compressed). This can be done with this
command:
$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
------------------------------------------------------------------------
Stefan Roese, 2012-08-23

479
board/a3m071/a3m071.c
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@ -1,479 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2006
* MicroSys GmbH
*
* Copyright 2012-2013 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <miiphy.h>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
#ifdef CONFIG_A4M2K
#include "is46r16320d.h"
#else
#include "mt46v16m16-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_SYS_RAMBOOT) && \
(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
static void sdram_start(int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
long control = SDRAM_CONTROL | hi_addr_bit;
/* unlock mode register */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
/* precharge all banks */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
#ifdef SDRAM_DDR
/* set mode register: extended mode */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
/* set mode register: reset DLL */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
#endif
/* precharge all banks */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
/* auto refresh */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
/* set mode register */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
/* normal operation */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
/*
* Wait a short while for the DLL to lock before accessing
* the SDRAM
*/
udelay(100);
}
#endif
/*
* ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
#if !defined(CONFIG_SYS_RAMBOOT) && \
(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
ulong test1, test2;
/* setup SDRAM chip selects */
out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
/* setup config registers */
out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
#ifdef SDRAM_DDR
/* set tap delay */
out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
0x13 + __builtin_ffs(dramsize >> 20) - 1);
} else {
out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
gd->ram_size = dramsize + dramsize2;
return 0;
}
static void get_revisions(int *failsavelevel, int *digiboardversion,
int *fpgaversion)
{
struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
u8 val;
/* read digitalboard-version from TMR[2..4] */
val = 0;
val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
*digiboardversion = val;
/*
* A4M2K only supports digiboardversion. No failsavelevel and
* fpgaversion here.
*/
#if !defined(CONFIG_A4M2K)
/*
* Figure out failsavelevel
* see ticket dsvk#59
*/
*failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
if (*digiboardversion == 0) {
*failsavelevel = 1; /* digiboard-version ok */
/* read fpga-version from TMR[5..7] */
val = 0;
val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
*fpgaversion = val;
if (*fpgaversion == 1)
*failsavelevel = 2; /* fpga-version ok */
}
#endif
}
/*
* This function is called from the SPL U-Boot version for
* early init stuff, that needs to be done for OS (e.g. Linux)
* booting. Doing it later in the real U-Boot would not work
* in case that the SPL U-Boot boots Linux directly.
*/
void spl_board_init(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
#if defined(CONFIG_A4M2K)
/* enable CS3 and CS5 (FPGA) */
setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
#else
int digiboardversion;
int failsavelevel;
int fpgaversion;
u32 val;
get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
val = in_be32(&mm->ipbi_ws_ctrl);
/* first clear bits 19..21 (CS3...5) */
val &= ~((1 << 19) | (1 << 20) | (1 << 21));
if (failsavelevel == 2) {
/* FPGA ok */
val |= (1 << 19) | (1 << 21);
}
if (failsavelevel >= 1) {
/* at least digiboard-version ok */
val |= (1 << 20);
}
/* And write new value back to register */
out_be32(&mm->ipbi_ws_ctrl, val);
/* Setup pin multiplexing */
if (failsavelevel == 2) {
/* fpga-version ok */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
#endif
} else if (failsavelevel == 1) {
/* digiboard-version ok - fpga not */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
#endif
} else {
/* full failsave-mode */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif
}
#endif
/*
* Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
* ticket #60
*
* MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
* set bit 0(msb) to 1
*/
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
#if defined(CONFIG_A4M2K)
/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
gpio->simple_ddr |= 1 << (31 - 15);
gpio->simple_ddr |= 1 << (31 - 14);
gpio->simple_ddr |= 1 << (31 - 13);
gpio->simple_ddr |= 1 << (31 - 12);
/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
gpio->simple_gpioe |= 1 << (31 - 15);
gpio->simple_gpioe |= 1 << (31 - 14);
gpio->simple_gpioe |= 1 << (31 - 13);
gpio->simple_gpioe |= 1 << (31 - 12);
/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
/* set PSC2[0..2] (STSLED[0..2]) direction to output */
gpio->simple_ddr |= 1 << (31 - 27);
gpio->simple_ddr |= 1 << (31 - 26);
gpio->simple_ddr |= 1 << (31 - 25);
/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
gpio->simple_gpioe |= 1 << (31 - 27);
gpio->simple_gpioe |= 1 << (31 - 26);
gpio->simple_gpioe |= 1 << (31 - 25);
/* Setup PSC6[2] as MRST2 self reset GPIO output */
/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
gpio->simple_ddr |= 1 << (31 - 3);
/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
gpio->simple_ode |= 1 << (31 - 3);
/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
gpio->simple_dvo |= 1 << (31 - 3);
/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
gpio->simple_gpioe |= 1 << (31 - 3);
/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
gpio->simple_ddr |= 0 << (31 - 2);
/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
gpio->simple_gpioe |= 1 << (31 - 2);
#else
/* setup GPIOs for status-leds if needed - see ticket #57 */
if (failsavelevel > 0) {
/* digiboard-version is OK */
/* LED is LOW ACTIVE - so deactivate by set output to 1 */
gpio->simple_dvo |= 1 << (31 - 12);
gpio->simple_dvo |= 1 << (31 - 13);
/* set GPIO direction to output */
gpio->simple_ddr |= 1 << (31 - 12);
gpio->simple_ddr |= 1 << (31 - 13);
/* open drain config is set to "normal output" at reset */
/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
/* enable as GPIO */
gpio->simple_gpioe |= 1 << (31 - 12);
gpio->simple_gpioe |= 1 << (31 - 13);
}
/* setup fpga irq - see ticket #65 */
if (failsavelevel > 1) {
/*
* The main irq initialisation is done in interrupts.c
* mpc5xxx_init_irq
*/
struct mpc5xxx_intr *intr =
(struct mpc5xxx_intr *)(MPC5XXX_ICTL);
setbits_be32(&intr->ctrl, 0x08C01801);
/*
* The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
* already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
*/
}
#endif
}
int checkboard(void)
{
int digiboardversion;
int failsavelevel;
int fpgaversion;
get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
#ifdef CONFIG_A4M2K
puts("Board: A4M2K\n");
printf(" digiboard IO version %u\n", digiboardversion);
#else
puts("Board: A3M071\n");
printf("Rev: failsave level %u\n", failsavelevel);
printf(" digiboard IO version %u\n", digiboardversion);
if (failsavelevel > 0) /* only if fpga-version red */
printf(" fpga IO version %u\n", fpgaversion);
#endif
return 0;
}
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
/* adjust flash start and offset to detected values */
gd->bd->bi_flashstart = flash_info[0].start[0];
gd->bd->bi_flashoffset = 0;
/* adjust mapping */
out_be32((void *)MPC5XXX_BOOTCS_START,
START_REG(gd->bd->bi_flashstart));
out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
out_be32((void *)MPC5XXX_BOOTCS_STOP,
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
out_be32((void *)MPC5XXX_CS0_STOP,
STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_SPL_OS_BOOT
/*
* A3M071 specific implementation of spl_start_uboot()
*
* RETURN
* 0 if booting into OS is selected (default)
* 1 if booting into U-Boot is selected
*/
int spl_start_uboot(void)
{
char s[8];
env_init();
getenv_f("boot_os", s, sizeof(s));
if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
*s == 't' || *s == 'T'))
return 0;
return 1;
}
#endif
#if defined(CONFIG_HW_WATCHDOG)
static int watchdog_toggle;
void hw_watchdog_reset(void)
{
int val;
/*
* Check if watchdog is enabled via user command
*/
if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
/* Set direction to output */
setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
/*
* Toggle watchdog output
*/
val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
CONFIG_WDOG_GPIO_PIN);
if (val) {
clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
CONFIG_WDOG_GPIO_PIN);
} else {
setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
CONFIG_WDOG_GPIO_PIN);
}
}
}
int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
goto usage;
if (strncmp(argv[1], "on", 2) == 0)
watchdog_toggle = 1;
else if (strncmp(argv[1], "off", 3) == 0)
watchdog_toggle = 0;
else
goto usage;
return 0;
usage:
printf("Usage: wdogtoggle %s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
"toggle GPIO pin to service watchdog",
"[on/off] - Switch watchdog toggling via GPIO pin on/off"
);
#endif

24
board/a3m071/is46r16320d.h
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@ -1,24 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
/* SDRAM Config Standard timing */
#define SDRAM_MODE 0x008d0000
#define SDRAM_EMODE 0x40010000
#define SDRAM_CONTROL 0x70430f00
#define SDRAM_CONFIG1 0x33622930
#define SDRAM_CONFIG2 0x46670000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

21
board/a3m071/mt46v16m16-75.h
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@ -1,21 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x704f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

9
board/a4m072/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_A4M072
config SYS_BOARD
default "a4m072"
config SYS_CONFIG_NAME
default "a4m072"
endif

6
board/a4m072/MAINTAINERS
View File

@ -1,6 +0,0 @@
A4M072 BOARD
M: Sergei Poselenov <sposelenov@emcraft.com>
S: Maintained
F: board/a4m072/
F: include/configs/a4m072.h
F: configs/a4m072_defconfig

8
board/a4m072/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := a4m072.o

479
board/a4m072/a4m072.c
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@ -1,479 +0,0 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2010
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <libfdt.h>
#include <netdev.h>
#include <led-display.h>
#include <linux/err.h>
#include "mt46v32m16.h"
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
long control = SDRAM_CONTROL | hi_addr_bit;
/* unlock mode register */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
__asm__ volatile ("sync");
/* precharge all banks */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
__asm__ volatile ("sync");
/* set mode register: reset DLL */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
__asm__ volatile ("sync");
#endif
/* precharge all banks */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
__asm__ volatile ("sync");
/* auto refresh */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
__asm__ volatile ("sync");
/* set mode register */
out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
__asm__ volatile ("sync");
/* normal operation */
out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
int dram_init(void)
{
ulong dramsize = 0;
uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
0x13 + __builtin_ffs(dramsize >> 20) - 1);
} else {
out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
__asm__ volatile ("sync");
}
gd->ram_size = dramsize;
return 0;
}
int checkboard (void)
{
puts ("Board: A4M072\n");
return 0;
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
int board_eth_init(bd_t *bis)
{
int rv, num_if = 0;
/* Initialize TSECs first */
if ((rv = cpu_eth_init(bis)) >= 0)
num_if += rv;
else
printf("ERROR: failed to initialize FEC.\n");
if ((rv = pci_eth_init(bis)) >= 0)
num_if += rv;
else
printf("ERROR: failed to initialize PCI Ethernet.\n");
return num_if;
}
/*
* Miscellaneous late-boot configurations
*
* Initialize EEPROM write-protect GPIO pin.
*/
int misc_init_r(void)
{
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Enable GPIO pin */
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
/* Set direction, output */
setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
/* De-assert write enable */
setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
#endif
return 0;
}
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
* 1: enable write
* Returns: -1: wrong device address
* 0: dis-/en- able done
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access */
clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access */
setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
CONFIG_SYS_EEPROM_WP));
break;
}
}
return state;
}
#endif
#ifdef CONFIG_CMD_DISPLAY
#define DISPLAY_BUF_SIZE 2
static u8 display_buf[DISPLAY_BUF_SIZE];
static u8 display_putc_pos;
static u8 display_out_pos;
void display_set(int cmd) {
if (cmd & DISPLAY_CLEAR) {
display_buf[0] = display_buf[1] = 0;
}
if (cmd & DISPLAY_HOME) {
display_putc_pos = 0;
}
}
#define SEG_A (1<<0)
#define SEG_B (1<<1)
#define SEG_C (1<<2)
#define SEG_D (1<<3)
#define SEG_E (1<<4)
#define SEG_F (1<<5)
#define SEG_G (1<<6)
#define SEG_P (1<<7)
#define SEG__ 0
/*
* +- A -+
* | |
* F B
* | |
* +- G -+
* | |
* E C
* | |
* +- D -+ P
*
* 0..9 index 0..9
* A..Z index 10..35
* - index 36
* _ index 37
* . index 38
*/
#define SYMBOL_DASH (36)
#define SYMBOL_UNDERLINE (37)
#define SYMBOL_DOT (38)
static u8 display_char2seg7_tbl[]=
{
SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
SEG_B | SEG_C, /* 1 */
SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
SEG_A | SEG_B | SEG_C, /* 7 */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
SEG_A | SEG_D | SEG_E | SEG_F, /* C */
SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
SEG_A | SEG_E | SEG_F | SEG_G, /* F */
0, /* g - not displayed */
SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
SEG_B | SEG_C, /* I */
0, /* J - not displayed */
0, /* K - not displayed */
SEG_D | SEG_E | SEG_F, /* L */
0, /* m - not displayed */
0, /* n - not displayed */
SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
0, /* q - not displayed */
0, /* r - not displayed */
SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
SEG_D | SEG_E | SEG_F | SEG_G, /* t */
SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
0, /* V - not displayed */
0, /* w - not displayed */
0, /* X - not displayed */
SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
0, /* Z - not displayed */
SEG_G, /* - */
SEG_D, /* _ */
SEG_P /* . */
};
/* Convert char to the LED segments representation */
static u8 display_char2seg7(char c)
{
u8 val = 0;
if (c >= '0' && c <= '9')
c -= '0';
else if (c >= 'a' && c <= 'z')
c -= 'a' - 10;
else if (c >= 'A' && c <= 'Z')
c -= 'A' - 10;
else if (c == '-')
c = SYMBOL_DASH;
else if (c == '_')
c = SYMBOL_UNDERLINE;
else if (c == '.')
c = SYMBOL_DOT;
else
c = ' '; /* display unsupported symbols as space */
if (c != ' ')
val = display_char2seg7_tbl[(int)c];
return val;
}
int display_putc(char c)
{
if (display_putc_pos >= DISPLAY_BUF_SIZE)
return -1;
display_buf[display_putc_pos++] = display_char2seg7(c);
/* one-symbol message should be steady */
if (display_putc_pos == 1)
display_buf[display_putc_pos] = display_char2seg7(c);
return c;
}
/*
* Flush current symbol to the LED display hardware
*/
static inline void display_flush(void)
{
u32 val = display_buf[display_out_pos];
val |= (val << 8) | (val << 16) | (val << 24);
out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
}
/*
* Output contents of the software display buffer to the LED display every 0.5s
*/
void board_show_activity(ulong timestamp)
{
static ulong last;
static u8 once;
if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
display_flush();
display_out_pos ^= 1;
last = timestamp;
once = 1;
}
}
/*
* Empty fake function
*/
void show_activity(int arg)
{
}
#endif
#if defined (CONFIG_SHOW_BOOT_PROGRESS)
static int a4m072_status2code(int status, char *buf)
{
char c = 0;
if (((status > 0) && (status <= 8)) ||
((status >= 100) && (status <= 108)) ||
((status < 0) && (status >= -9)) ||
(status == -100) || (status == -101) ||
((status <= -103) && (status >= -113))) {
c = '5';
} else if (((status >= 9) && (status <= 14)) ||
((status >= 120) && (status <= 123)) ||
((status >= 125) && (status <= 129)) ||
((status >= -13) && (status <= -10)) ||
(status == -120) || (status == -122) ||
((status <= -124) && (status >= -127)) ||
(status == -129)) {
c = '8';
} else if (status == 15) {
c = '9';
} else if ((status <= -30) && (status >= -32)) {
c = 'A';
} else if (((status <= -35) && (status >= -40)) ||
((status <= -42) && (status >= -51)) ||
((status <= -53) && (status >= -58)) ||
(status == -64) ||
((status <= -80) && (status >= -83)) ||
(status == -130) || (status == -140) ||
(status == -150)) {
c = 'B';
}
if (c == 0)
return -EINVAL;
buf[0] = (status < 0) ? '-' : c;
buf[1] = c;
return 0;
}
void show_boot_progress(int status)
{
char buf[2];
if (a4m072_status2code(status, buf) < 0)
return;
display_putc(buf[0]);
display_putc(buf[1]);
display_set(DISPLAY_HOME);
display_out_pos = 0; /* reset output position */
/* we want to flush status 15 now */
if (status == BOOTSTAGE_ID_RUN_OS)
display_flush();
}
#endif

21
board/a4m072/mt46v32m16.h
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@ -1,21 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40010000
#define SDRAM_CONTROL 0x704f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

9
board/canmb/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_CANMB
config SYS_BOARD
default "canmb"
config SYS_CONFIG_NAME
default "canmb"
endif

6
board/canmb/MAINTAINERS
View File

@ -1,6 +0,0 @@
CANMB BOARD
#M: -
S: Maintained
F: board/canmb/
F: include/configs/canmb.h
F: configs/canmb_defconfig

9
board/canmb/Makefile
View File

@ -1,9 +0,0 @@
#
# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := canmb.o

187
board/canmb/canmb.c
View File

@ -1,187 +0,0 @@
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m32s2-75.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
int dram_init(void)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20)) {
dramsize2 = 0;
}
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
} else {
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CONFIG_SYS_RAMBOOT */
gd->ram_size = dramsize + dramsize2;
return 0;
}
int checkboard (void)
{
puts ("Board: CANMB\n");
return 0;
}
int board_early_init_r (void)
{
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
*(vu_long *)MPC5XXX_BOOTCS_START =
*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
*(vu_long *)MPC5XXX_BOOTCS_STOP =
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
return 0;
}

14
board/canmb/mt48lc16m32s2-75.h
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@ -1,14 +0,0 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define SDRAM_DDR 0 /* is SDR */
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000

9
board/cm5200/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_CM5200
config SYS_BOARD
default "cm5200"
config SYS_CONFIG_NAME
default "cm5200"
endif

6
board/cm5200/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM5200 BOARD
#M: -
S: Maintained
F: board/cm5200/
F: include/configs/cm5200.h
F: configs/cm5200_defconfig

8
board/cm5200/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2003-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := cm5200.o cmd_cm5200.o fwupdate.o

355
board/cm5200/cm5200.c
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@ -1,355 +0,0 @@
/*
* (C) Copyright 2003-2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2004-2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* Adapted to U-Boot 1.2 by:
* Bartlomiej Sieka <tur@semihalf.com>:
* - HW ID readout from EEPROM
* - module detection
* Grzegorz Bernacki <gjb@semihalf.com>:
* - run-time SDRAM controller configuration
* - LIBFDT support
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#include <i2c.h>
#include <linux/ctype.h>
#ifdef CONFIG_OF_LIBFDT
#include <libfdt.h>
#include <fdt_support.h>
#endif /* CONFIG_OF_LIBFDT */
#include "cm5200.h"
#include "fwupdate.h"
DECLARE_GLOBAL_DATA_PTR;
static hw_id_t hw_id;
#ifndef CONFIG_SYS_RAMBOOT
/*
* Helper function to initialize SDRAM controller.
*/
static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
hi_addr_bit;
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
hi_addr_bit;
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
hi_addr_bit;
/* auto refresh, second time */
*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
hi_addr_bit;
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
}
#endif /* CONFIG_SYS_RAMBOOT */
/*
* Retrieve memory configuration for a given module. board_type is the index
* in hw_id_list[] corresponding to the module we are executing on; we return
* SDRAM controller settings approprate for this module.
*/
static mem_conf_t* get_mem_config(int board_type)
{
switch(board_type){
case CM1_QA:
return memory_config[0];
case CM11_QA:
case CMU1_QA:
return memory_config[1];
default:
printf("ERROR: Unknown module, using a default SDRAM "
"configuration - things may not work!!!.\n");
return memory_config[0];
}
}
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
int dram_init(void)
{
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
mem_conf_t *mem_conf;
mem_conf = get_mem_config(gd->board_type);
/* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
sdram_start(0, mem_conf);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1, mem_conf);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0, mem_conf);
dramsize = test1;
} else
dramsize = test2;
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
__builtin_ffs(dramsize >> 20) - 1;
} else
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
#endif /* !CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
* the MPC5200B User's Manual.
*/
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
__asm__ volatile ("sync");
gd->ram_size = dramsize;
return 0;
}
/*
* Read module hardware identification data from the I2C EEPROM.
*/
static void read_hw_id(hw_id_t hw_id)
{
printf("ERROR: can't read HW ID from EEPROM\n");
}
/*
* Identify module we are running on, set gd->board_type to the index in
* hw_id_list[] corresponding to the module identifed, or to
* CM5200_UNKNOWN_MODULE if we can't identify the module.
*/
static void identify_module(hw_id_t hw_id)
{
int i, j, element;
char match;
gd->board_type = CM5200_UNKNOWN_MODULE;
for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
match = 1;
for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
element = hw_id_identify[j];
if (strncmp(hw_id_list[i][element],
&hw_id[element][0],
hw_id_format[element].length) != 0) {
match = 0;
break;
}
}
if (match) {
gd->board_type = i;
break;
}
}
}
/*
* Compose string with module name.
* buf is assumed to have enough space, and be null-terminated.
*/
static void compose_module_name(hw_id_t hw_id, char *buf)
{
char tmp[MODULE_NAME_MAXLEN];
strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
strncat(buf, ".", 1);
strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
strncat(buf, " (", 2);
strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
hw_id_format[IDENTIFICATION_NUMBER].length);
sprintf(tmp, " / %u.%u)",
hw_id[MAJOR_SW_VERSION][0],
hw_id[MINOR_SW_VERSION][0]);
strcat(buf, tmp);
}
#if defined(CONFIG_SYS_I2C_SOFT)
/*
* Compose string with hostname.
* buf is assumed to have enough space, and be null-terminated.
*/
static void compose_hostname(hw_id_t hw_id, char *buf)
{
char *p;
strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
strncat(buf, "_", 1);
strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
for (p = buf; *p; ++p)
*p = tolower(*p);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
/*
* Update 'model' and 'memory' properties in the blob according to the module
* that we are running on.
*/
static void ft_blob_update(void *blob, bd_t *bd)
{
int len, ret, nodeoffset = 0;
char module_name[MODULE_NAME_MAXLEN] = {0};
compose_module_name(hw_id, module_name);
len = strlen(module_name) + 1;
ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
if (ret < 0)
printf("ft_blob_update(): cannot set /model property err:%s\n",
fdt_strerror(ret));
}
#endif /* CONFIG_OF_BOARD_SETUP */
/*
* Read HW ID from I2C EEPROM and detect the modue we are running on. Note
* that we need to use local variable for readout, because global data is not
* writable yet (and we'll have to redo the readout later on).
*/
int checkboard(void)
{
hw_id_t hw_id_tmp;
char module_name_tmp[MODULE_NAME_MAXLEN] = "";
read_hw_id(hw_id_tmp);
identify_module(hw_id_tmp); /* this sets gd->board_type */
compose_module_name(hw_id_tmp, module_name_tmp);
if (gd->board_type != CM5200_UNKNOWN_MODULE)
printf("Board: %s\n", module_name_tmp);
else
printf("Board: unrecognized cm5200 module (%s)\n",
module_name_tmp);
return 0;
}
int board_early_init_r(void)
{
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in
* flash.
*/
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
/* Now that we can write to global data, read HW ID again. */
read_hw_id(hw_id);
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#if defined(CONFIG_SYS_I2C_SOFT)
uchar buf[6];
char str[18];
char hostname[MODULE_NAME_MAXLEN];
/* Read ethaddr from EEPROM */
if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
/* Check if MAC addr is owned by Schindler */
if (strstr(str, "00:06:C3") != str)
printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
" in EEPROM.\n", str);
else {
printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
str);
setenv("ethaddr", str);
}
} else {
printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
CONFIG_MAC_OFFSET);
}
hostname[0] = 0x00;
/* set the hostname appropriate to the module we're running on */
compose_hostname(hw_id, hostname);
setenv("hostname", hostname);
#endif /* defined(CONFIG_SYS_I2C_SOFT) */
if (!getenv("ethaddr"))
printf(LOG_PREFIX "MAC address not set, networking is not "
"operational\n");
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_LAST_STAGE_INIT
int last_stage_init(void)
{
#ifdef CONFIG_USB_STORAGE
cm5200_fwupdate();
#endif /* CONFIG_USB_STORAGE */
return 0;
}
#endif /* CONFIG_LAST_STAGE_INIT */
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
ft_blob_update(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

171
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@ -1,171 +0,0 @@
/*
* (C) Copyright 2007 DENX Software Engineering
*
* Author: Bartlomiej Sieka <tur@semihalf.com>
* Author: Grzegorz Bernacki <gjb@semihalf.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CM5200_H
#define _CM5200_H
/*
* Definitions and declarations for the modules of the cm5200 platform. Mostly
* related to reading the hardware identification data (HW ID) from the I2C
* EEPROM, detection of the particular module we are executing on, and
* appropriate SDRAM controller initialization.
*/
#define CM5200_UNKNOWN_MODULE 0xffffffff
enum {
DEVICE_NAME, /* 0 */
GENERATION, /* 1 */
PCB_NAME, /* 2 */
FORM, /* 3 */
VERSION, /* 4 */
IDENTIFICATION_NUMBER, /* 5 */
MAJOR_SW_VERSION, /* 6 */
MINOR_SW_VERSION, /* 7 */
/* add new alements above this line */
HW_ID_ELEM_COUNT /* count */
};
/*
* Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
*/
#define DEVICE_NAME_OFFSET 0x02
#define GENERATION_OFFSET 0x0b
#define PCB_NAME_OFFSET 0x0c
#define FORM_OFFSET 0x15
#define VERSION_OFFSET 0x16
#define IDENTIFICATION_NUMBER_OFFSET 0x19
#define MAJOR_SW_VERSION_OFFSET 0x0480
#define MINOR_SW_VERSION_OFFSET 0x0481
#define DEVICE_NAME_LEN 0x09
#define GENERATION_LEN 0x01
#define PCB_NAME_LEN 0x09
#define FORM_LEN 0x01
#define VERSION_LEN 0x03
#define IDENTIFICATION_NUMBER_LEN 0x09
#define MAJOR_SW_VERSION_LEN 0x01
#define MINOR_SW_VERSION_LEN 0x01
#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
#define MODULE_NAME_MAXLEN 64
/* storage for HW ID read from EEPROM */
typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
/* HW ID layout in EEPROM */
static struct {
unsigned int offset;
unsigned int length;
} hw_id_format[HW_ID_ELEM_COUNT] = {
{DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
{GENERATION_OFFSET, GENERATION_LEN},
{PCB_NAME_OFFSET, PCB_NAME_LEN},
{FORM_OFFSET, FORM_LEN},
{VERSION_OFFSET, VERSION_LEN},
{IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
{MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
{MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
};
/* HW ID data found in EEPROM on supported modules */
static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
"CM", /* DEVICE_NAME */
"1", /* GENERATION */
"CM1", /* PCB_NAME */
"Q", /* FORM */
"A", /* VERSION */
"591881", /* IDENTIFICATION_NUMBER */
"", /* MAJOR_SW_VERSION */
"", /* MINOR_SW_VERSION */
};
static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
"CM", /* DEVICE_NAME */
"1", /* GENERATION */
"CM11", /* PCB_NAME */
"Q", /* FORM */
"A", /* VERSION */
"594200", /* IDENTIFICATION_NUMBER */
"", /* MAJOR_SW_VERSION */
"", /* MINOR_SW_VERSION */
};
static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
"CMU", /* DEVICE_NAME */
"1", /* GENERATION */
"CMU1", /* PCB_NAME */
"Q", /* FORM */
"A", /* VERSION */
"594128", /* IDENTIFICATION_NUMBER */
"", /* MAJOR_SW_VERSION */
"", /* MINOR_SW_VERSION */
};
/* list of known modules */
static char **hw_id_list[] = {
cm1_qa_hw_id,
cm11_qa_hw_id,
cmu1_qa_hw_id,
};
/* indices to the above list - keep in sync */
enum {
CM1_QA,
CM11_QA,
CMU1_QA,
};
/* identify modules based on these hw id elements */
static int hw_id_identify[] = {
PCB_NAME,
FORM,
VERSION,
};
/* Registers' settings for SDRAM controller intialization */
typedef struct {
ulong mode;
ulong control;
ulong config1;
ulong config2;
} mem_conf_t;
static mem_conf_t k4s561632E = {
0x00CD0000, /* CASL 3, burst length 8 */
0x514F0000,
0xE2333900,
0x8EE70000
};
static mem_conf_t mt48lc32m16a2 = {
0x00CD0000, /* CASL 3, burst length 8 */
0x514F0000,
0xD2322800,
0x8AD70000
};
static mem_conf_t* memory_config[] = {
&k4s561632E,
&mt48lc32m16a2
};
#endif /* _CM5200_H */

402
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/*
* (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
*
* Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <usb.h>
#ifdef CONFIG_CMD_BSP
static int do_usb_test(char * const argv[])
{
int i;
static int usb_stor_curr_dev = -1; /* current device */
printf("Starting USB Test\n"
"Please insert USB Memmory Stick\n\n"
"Please press any key to start\n\n");
getc();
usb_stop();
printf("(Re)start USB...\n");
i = usb_init();
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
if (i >= 0)
usb_stor_curr_dev = usb_stor_scan(1);
#endif /* CONFIG_USB_STORAGE */
if (usb_stor_curr_dev >= 0)
printf("Found USB Storage Dev continue with Test...\n");
else {
printf("No USB Storage Device detected.. Stop Test\n");
return 1;
}
usb_stor_info();
printf("stopping USB..\n");
usb_stop();
return 0;
}
static int do_led_test(char * const argv[])
{
int i = 0;
struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
printf("Starting LED Test\n"
"Please set Switch S500 all off\n\n"
"Please press any key to start\n\n");
getc();
/* configure timer 2-3 for simple GPIO output High */
gpt->gpt2.emsr |= 0x00000034;
gpt->gpt3.emsr |= 0x00000034;
(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
printf("Please press any key to stop\n\n");
while (!tstc()) {
if (i == 1) {
(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
gpt->gpt2.emsr &= ~0x00000010;
gpt->gpt3.emsr &= ~0x00000010;
} else if (i == 2) {
(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
gpt->gpt2.emsr &= ~0x00000010;
gpt->gpt3.emsr |= 0x00000010;
} else if (i >= 3) {
(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
gpt->gpt3.emsr &= ~0x00000010;
gpt->gpt2.emsr |= 0x00000010;
i = 0;
}
i++;
udelay(200000);
}
getc();
(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
gpt->gpt2.emsr |= 0x00000010;
gpt->gpt3.emsr |= 0x00000010;
return 0;
}
static int do_rs232_test(char * const argv[])
{
int error_status = 0;
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
/* Configure PSC 2-3-6 as GPIO */
gpio->port_config &= 0xFF0FF80F;
switch (simple_strtoul(argv[2], NULL, 10)) {
case 1:
/* check RTS <-> CTS loop */
/* set rts to 0 */
printf("Uart 1 test: RX TX tested by using U-Boot\n"
"Please connect RTS with CTS on Uart1 plug\n\n"
"Press any key to start\n\n");
getc();
psc1->op1 |= 0x01;
/* wait some time before requesting status */
udelay(10);
/* check status at cts */
if ((psc1->ip & 0x01) != 0) {
error_status = 3;
printf("%s: failure at rs232_1, cts status is %d "
"(should be 0)\n",
__FUNCTION__, (psc1->ip & 0x01));
}
/* set rts to 1 */
psc1->op0 |= 0x01;
/* wait some time before requesting status */
udelay(10);
/* check status at cts */
if ((psc1->ip & 0x01) != 1) {
error_status = 3;
printf("%s: failure at rs232_1, cts status is %d "
"(should be 1)\n",
__FUNCTION__, (psc1->ip & 0x01));
}
break;
case 2:
/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
"\nPress any key to start\n\n");
getc();
gpio->simple_gpioe &= ~(0x000000F0);
gpio->simple_gpioe |= 0x000000F0;
gpio->simple_ddr &= ~(0x000000F0);
gpio->simple_ddr |= 0x00000050;
/* check TXD <-> RXD loop */
/* set TXD to 1 */
gpio->simple_dvo |= (1 << 4);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
error_status = 2;
printf("%s: failure at rs232_2, rxd status is %d "
"(should be 1)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000020) >> 5);
}
/* set TXD to 0 */
gpio->simple_dvo &= ~(1 << 4);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
error_status = 2;
printf("%s: failure at rs232_2, rxd status is %d "
"(should be 0)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000020) >> 5);
}
/* check RTS <-> CTS loop */
/* set RTS to 1 */
gpio->simple_dvo |= (1 << 6);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
error_status = 3;
printf("%s: failure at rs232_2, cts status is %d "
"(should be 1)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000080) >> 7);
}
/* set RTS to 0 */
gpio->simple_dvo &= ~(1 << 6);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
error_status = 3;
printf("%s: failure at rs232_2, cts status is %d "
"(should be 0)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000080) >> 7);
}
break;
case 3:
/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
"\nPress any key to start\n\n");
getc();
gpio->simple_gpioe &= ~(0x00000F00);
gpio->simple_gpioe |= 0x00000F00;
gpio->simple_ddr &= ~(0x00000F00);
gpio->simple_ddr |= 0x00000500;
/* check TXD <-> RXD loop */
/* set TXD to 1 */
gpio->simple_dvo |= (1 << 8);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
error_status = 2;
printf("%s: failure at rs232_3, rxd status is %d "
"(should be 1)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000200) >> 9);
}
/* set TXD to 0 */
gpio->simple_dvo &= ~(1 << 8);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
error_status = 2;
printf("%s: failure at rs232_3, rxd status is %d "
"(should be 0)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000200) >> 9);
}
/* check RTS <-> CTS loop */
/* set RTS to 1 */
gpio->simple_dvo |= (1 << 10);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
error_status = 3;
printf("%s: failure at rs232_3, cts status is %d "
"(should be 1)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000800) >> 11);
}
/* set RTS to 0 */
gpio->simple_dvo &= ~(1 << 10);
/* wait some time before requesting status */
udelay(10);
if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
error_status = 3;
printf("%s: failure at rs232_3, cts status is %d "
"(should be 0)\n", __FUNCTION__,
(gpio->simple_ival & 0x00000800) >> 11);
}
break;
case 4:
/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
"\nPress any key to start\n\n");
getc();
gpio->simple_gpioe &= ~(0xF0000000);
gpio->simple_gpioe |= 0x30000000;
gpio->simple_ddr &= ~(0xf0000000);
gpio->simple_ddr |= 0x30000000;
(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
/* check TXD <-> RXD loop */
/* set TXD to 1 */
gpio->simple_dvo |= (1 << 28);
/* wait some time before requesting status */
udelay(10);
if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
0x10000000) {
error_status = 2;
printf("%s: failure at rs232_4, rxd status is %lu "
"(should be 1)\n", __FUNCTION__,
((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
0x10000000) >> 28);
}
/* set TXD to 0 */
gpio->simple_dvo &= ~(1 << 28);
/* wait some time before requesting status */
udelay(10);
if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
0x00000000) {
error_status = 2;
printf("%s: failure at rs232_4, rxd status is %lu "
"(should be 0)\n", __FUNCTION__,
((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
0x10000000) >> 28);
}
/* check RTS <-> CTS loop */
/* set RTS to 1 */
gpio->simple_dvo |= (1 << 29);
/* wait some time before requesting status */
udelay(10);
if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
0x20000000) {
error_status = 3;
printf("%s: failure at rs232_4, cts status is %lu "
"(should be 1)\n", __FUNCTION__,
((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
0x20000000) >> 29);
}
/* set RTS to 0 */
gpio->simple_dvo &= ~(1 << 29);
/* wait some time before requesting status */
udelay(10);
if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
0x00000000) {
error_status = 3;
printf("%s: failure at rs232_4, cts status is %lu "
"(should be 0)\n", __FUNCTION__,
((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
0x20000000) >> 29);
}
break;
default:
printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
error_status = 1;
break;
}
gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
return error_status;
}
static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = -1;
switch (argc) {
case 2:
if (strncmp(argv[1], "led", 3) == 0)
rcode = do_led_test(argv);
else if (strncmp(argv[1], "usb", 3) == 0)
rcode = do_usb_test(argv);
break;
case 3:
if (strncmp(argv[1], "rs232", 3) == 0)
rcode = do_rs232_test(argv);
break;
}
switch (rcode) {
case -1:
printf("Usage:\n"
"fkt { i2c | led | usb }\n"
"fkt rs232 number\n");
rcode = 1;
break;
case 0:
printf("Test passed\n");
break;
default:
printf("Test failed with code: %d\n", rcode);
}
return rcode;
}
U_BOOT_CMD(
fkt, 4, 1, cmd_fkt,
"Function test routines",
"i2c\n"
" - Test I2C communication\n"
"fkt led\n"
" - Test LEDs\n"
"fkt rs232 number\n"
" - Test RS232 (loopback plug(s) for RS232 required)\n"
"fkt usb\n"
" - Test USB communication"
);
#endif /* CONFIG_CMD_BSP */

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/*
* (C) Copyright 2007 Schindler Lift Inc.
* (C) Copyright 2007 DENX Software Engineering
*
* Author: Michel Marti <mma@objectxp.com>
* Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
* - code clean-up
* - bugfix for overwriting bootargs by user
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <fat.h>
#include <malloc.h>
#include <image.h>
#include <usb.h>
#include <fat.h>
#include "fwupdate.h"
static int load_rescue_image(ulong);
void cm5200_fwupdate(void)
{
cmd_tbl_t *bcmd;
char *rsargs;
char *tmp = NULL;
char ka[16];
char * const argv[3] = { "bootm", ka, NULL };
/* Check if rescue system is disabled... */
if (getenv("norescue")) {
printf(LOG_PREFIX "Rescue System disabled.\n");
return;
}
/* Check if we have a USB storage device and load image */
if (load_rescue_image(LOAD_ADDR))
return;
bcmd = find_cmd("bootm");
if (!bcmd)
return;
sprintf(ka, "%lx", (ulong)LOAD_ADDR);
/* prepare our bootargs */
rsargs = getenv("rs-args");
if (!rsargs)
rsargs = RS_BOOTARGS;
else {
tmp = malloc(strlen(rsargs+1));
if (!tmp) {
printf(LOG_PREFIX "Memory allocation failed\n");
return;
}
strcpy(tmp, rsargs);
rsargs = tmp;
}
setenv("bootargs", rsargs);
if (rsargs == tmp)
free(rsargs);
printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
do_bootm(bcmd, 0, 2, argv);
}
static int load_rescue_image(ulong addr)
{
disk_partition_t info;
int devno;
int partno;
int i;
char fwdir[64];
char nxri[128];
char *tmp;
char dev[7];
char addr_str[16];
char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
struct blk_desc *stor_dev = NULL;
cmd_tbl_t *bcmd;
/* Get name of firmware directory */
tmp = getenv("fw-dir");
/* Copy it into fwdir */
strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
" storage...\n", fwdir);
usb_stop();
if (usb_init() != 0)
return 1;
/* Check for storage device */
if (usb_stor_scan(1) != 0) {
usb_stop();
return 1;
}
/* Detect storage device */
for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
if (stor_dev->type != DEV_TYPE_UNKNOWN)
break;
}
if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
printf(LOG_PREFIX "No valid storage device found...\n");
usb_stop();
return 1;
}
/* Detect partition */
for (partno = -1, i = 0; i < 6; i++) {
if (part_get_info(stor_dev, i, &info) == 0) {
if (fat_register_device(stor_dev, i) == 0) {
/* Check if rescue image is present */
FW_DEBUG("Looking for firmware directory '%s'"
" on partition %d\n", fwdir, i);
if (!fat_exists(fwdir)) {
FW_DEBUG("No NX rescue image on "
"partition %d.\n", i);
partno = -2;
} else {
partno = i;
FW_DEBUG("Partition %d contains "
"firmware directory\n", partno);
break;
}
}
}
}
if (partno < 0) {
switch (partno) {
case -1:
printf(LOG_PREFIX "Error: No valid (FAT) partition "
"detected\n");
break;
case -2:
printf(LOG_PREFIX "Error: No NX rescue image on FAT "
"partition\n");
break;
default:
printf(LOG_PREFIX "Error: Failed with code %d\n",
partno);
}
usb_stop();
return 1;
}
/* Load the rescue image */
bcmd = find_cmd("fatload");
if (!bcmd) {
printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
usb_stop();
return 1;
}
tmp = getenv("nx-rescue-image");
sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
sprintf(dev, "%d:%d", devno, partno);
sprintf(addr_str, "%lx", addr);
FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
dev, addr_str, nxri);
if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
usb_stop();
return 1;
}
/* Stop USB */
usb_stop();
return 0;
}

31
board/cm5200/fwupdate.h
View File

@ -1,31 +0,0 @@
/*
* (C) Copyright 2007 Schindler Lift Inc.
*
* Author: Michel Marti <mma@objectxp.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FW_UPDATE_H
#define __FW_UPDATE_H
/* Default prefix for output messages */
#define LOG_PREFIX "CM5200:"
/* Extra debug macro */
#ifdef CONFIG_FWUPDATE_DEBUG
#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
#else
#define FW_DEBUG(fmt...)
#endif
/* Name of the directory holding firmware images */
#define FW_DIR "nx-fw"
#define RESCUE_IMAGE "nxrs.img"
#define LOAD_ADDR 0x400000
#define RS_BOOTARGS "ramdisk_size=8192K"
/* Main function for fwupdate */
void cm5200_fwupdate(void);
#endif /* __FW_UPDATE_H */

12
board/davedenx/aria/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_ARIA
config SYS_BOARD
default "aria"
config SYS_VENDOR
default "davedenx"
config SYS_CONFIG_NAME
default "aria"
endif

6
board/davedenx/aria/MAINTAINERS
View File

@ -1,6 +0,0 @@
ARIA BOARD
M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: board/davedenx/aria/
F: include/configs/aria.h
F: configs/aria_defconfig

7
board/davedenx/aria/Makefile
View File

@ -1,7 +0,0 @@
#
# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := aria.o

115
board/davedenx/aria/aria.c
View File

@ -1,115 +0,0 @@
/*
* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
* (C) Copyright 2009 Dave Srl www.dave.eu
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/bitops.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mpc512x.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = fixed_sdram(NULL, NULL, 0);
return 0;
}
int misc_init_r(void)
{
u32 tmp;
tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
printf("FPGA: %u-%u.%u.%u\n",
(tmp & 0xFF000000) >> 24,
(tmp & 0x00FF0000) >> 16,
(tmp & 0x0000FF00) >> 8,
tmp & 0x000000FF
);
return 0;
}
static iopin_t ioregs_init[] = {
/*
* FEC
*/
/* FEC on PSCx_x*/
{
offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
{
offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
{
offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/*
* DIU
*/
/* FUNC2=DIU CLK */
{
offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/*
* On board SRAM
*/
/* FUNC2=/LPC CS6 */
{
offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
};
int checkboard (void)
{
puts("Board: ARIA\n");
/* initialize function mux & slew rate IO inter alia on IO Pins */
iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

12
board/esd/mecp5123/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_MECP5123
config SYS_BOARD
default "mecp5123"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "mecp5123"
endif

6
board/esd/mecp5123/MAINTAINERS
View File

@ -1,6 +0,0 @@
MECP5123 BOARD
M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
S: Maintained
F: board/esd/mecp5123/
F: include/configs/mecp5123.h
F: configs/mecp5123_defconfig

7
board/esd/mecp5123/Makefile
View File

@ -1,7 +0,0 @@
#
# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mecp5123.o

200
board/esd/mecp5123/mecp5123.c
View File

@ -1,200 +0,0 @@
/*
* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
* (C) Copyright 2009 Dave Srl www.dave.eu
* (C) Copyright 2009 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/bitops.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mpc512x.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
int eeprom_write_enable(unsigned dev_addr, int state)
{
return -ENOSYS;
}
int board_early_init_f(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
int i;
/*
* Initialize Local Window for boot access
*/
out_be32(&im->sysconf.lpbaw,
CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
sync_law(&im->sysconf.lpbaw);
/*
* Configure MSCAN clocks
*/
for (i=0; i<4; ++i) {
out_be32(&im->clk.msccr[i], 0x00300000);
out_be32(&im->clk.msccr[i], 0x00310000);
}
/*
* Configure GPIO's
*/
clrbits_be32(&im->gpio.gpodr, 0x000000e0);
clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
setbits_be32(&im->gpio.gpdir, 0x001000e0);
setbits_be32(&im->gpio.gpdat, 0x00100000);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
return 0;
}
int misc_init_r(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 val;
/*
* Optimize access to profibus chip (VPC3) on the local bus
*/
/*
* Select 1:1 for LPC_DIV
*/
val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
/*
* Configure LPC Chips Select Deadcycle Control Register
* CS0 - device can drive data 2 clock cycle(s) after CS deassertion
* CS1 - device can drive data 1 clock cycle(s) after CS deassertion
*/
clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
/*
* Configure LPC Chips Select Holdcycle Control Register
* CS0 - data is valid 2 clock cycle(s) after CS deassertion
* CS1 - data is valid 1 clock cycle(s) after CS deassertion
*/
clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
return 0;
}
static iopin_t ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SELECT LPC_CS1 */
{
offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC5_2 */
{
offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC5_3 */
{
offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC7_3 */
{
offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC9_0 */
{
offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC10_0 */
{
offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC10_3 */
{
offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC3=SELECT PSC11_0 */
{
offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC0=SELECT IRQ0 */
{
offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
static iopin_t rev2_silicon_pci_ioregs_init[] = {
/* FUNC0=PCI Sets next 54 to PCI pads */
{
offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
}
};
int checkboard(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr;
puts("Board: MECP_5123\n");
/*
* Initialize function mux & slew rate IO inter alia on IO
* Pins
*/
iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
spridr = in_be32(&im->sysconf.spridr);
if (SVR_MJREV(spridr) >= 2)
iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

12
board/freescale/mpc5121ads/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_MPC5121ADS
config SYS_BOARD
default "mpc5121ads"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "mpc5121ads"
endif

7
board/freescale/mpc5121ads/MAINTAINERS
View File

@ -1,7 +0,0 @@
MPC5121ADS BOARD
#M: -
S: Maintained
F: board/freescale/mpc5121ads/
F: include/configs/mpc5121ads.h
F: configs/mpc5121ads_defconfig
F: configs/mpc5121ads_rev2_defconfig

8
board/freescale/mpc5121ads/Makefile
View File

@ -1,8 +0,0 @@
#
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mpc5121ads.o

7
board/freescale/mpc5121ads/README
View File

@ -1,7 +0,0 @@
To configure for the current (Rev 3.x) ADS5121
make mpc5121ads_config
This will automatically include PCI, the Real Time CLock, add backup flash
ability and set the correct frequency and memory configuration.
To configure for the older Rev 2 ADS5121 type (this will not have PCI)
make mpc5121ads_rev2_config

265
board/freescale/mpc5121ads/mpc5121ads.c
View File

@ -1,265 +0,0 @@
/*
* (C) Copyright 2007-2009 DENX Software Engineering
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/bitops.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mpc512x.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
#include <net.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
DECLARE_GLOBAL_DATA_PTR;
void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
extern int mpc5121_nfc_chip;
/* Control chips select signal on MPC5121ADS board */
void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
{
unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
u8 v;
v = in_8(csreg);
v |= 0x0F;
if (chip >= 0) {
__mpc5121_nfc_select_chip(mtd, 0);
v &= ~(1 << mpc5121_nfc_chip);
} else {
__mpc5121_nfc_select_chip(mtd, -1);
}
out_8(csreg, v);
}
int board_early_init_f(void)
{
/*
* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
*
* Without this the flash identification routine fails, as it needs to issue
* write commands in order to establish the device ID.
*/
#ifdef CONFIG_MPC5121ADS_REV2
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
#else
if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
} else {
/* running from Backup flash */
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
}
#endif
return 0;
}
int is_micron(void){
ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
uchar macaddr[6];
u32 brddate, macchk, ismicron;
/*
* MAC address has serial number with date of manufacture
* Boards made before Nov-08 #1180 use Micron memory;
* 001e59 is the STx vendor #
* Default is Elpida since it works for both but is slightly slower
*/
ismicron = 0;
if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
debug("brddate = %d\n\t", brddate);
if (macchk == 0x001e59 && brddate <= 8111180)
ismicron = 1;
} else if (brd_rev < 0x400) {
ismicron = 1;
}
debug("Using %s Memory settings\n\t",
ismicron ? "Micron" : "Elpida");
return(ismicron);
}
int dram_init(void)
{
u32 msize = 0;
/*
* Elpida MDDRC and initialization settings are an alternative
* to the Default Micron ones for all but the earliest Rev 4 boards
*/
ddr512x_config_t elpida_mddrc_config = {
.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
};
u32 elpida_init_sequence[] = {
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_EM2,
CONFIG_SYS_DDRCMD_EM3,
CONFIG_SYS_DDRCMD_EN_DLL,
CONFIG_SYS_ELPIDA_RES_DLL,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_ELPIDA_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_OCD_DEFAULT,
CONFIG_SYS_ELPIDA_OCD_EXIT,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP
};
if (is_micron()) {
msize = fixed_sdram(NULL, NULL, 0);
} else {
msize = fixed_sdram(&elpida_mddrc_config,
elpida_init_sequence,
sizeof(elpida_init_sequence)/sizeof(u32));
}
gd->ram_size = msize;
return 0;
}
int misc_init_r(void)
{
return 0;
}
static iopin_t ioregs_init[] = {
/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
{
offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* Set highest Slew on 9 PATA pins */
{
offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
{
offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC1=SPDIF_TXCLK */
{
offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
{
offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU CLK */
{
offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
},
/* FUNC2=DIU_HSYNC */
{
offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
},
/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
{
offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
}
};
static iopin_t rev2_silicon_pci_ioregs_init[] = {
/* FUNC0=PCI Sets next 54 to PCI pads */
{
offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
}
};
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 spridr = in_be32(&im->sysconf.spridr);
printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
if (SVR_MJREV (spridr) >= 2)
iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

12
board/ifm/ac14xx/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_AC14XX
config SYS_BOARD
default "ac14xx"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "ac14xx"
endif

6
board/ifm/ac14xx/MAINTAINERS
View File

@ -1,6 +0,0 @@
AC14XX BOARD
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
F: board/ifm/ac14xx/
F: include/configs/ac14xx.h
F: configs/ac14xx_defconfig

7
board/ifm/ac14xx/Makefile
View File

@ -1,7 +0,0 @@
#
# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ac14xx.o

569
board/ifm/ac14xx/ac14xx.c
View File

@ -1,569 +0,0 @@
/*
* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
* (C) Copyright 2009 Dave Srl www.dave.eu
* (C) Copyright 2010 ifm ecomatic GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/bitops.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mpc512x.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
static int mac_diag;
static int gpio_diag;
DECLARE_GLOBAL_DATA_PTR;
static void gpio_configure(void)
{
immap_t *im;
gpio512x_t *gpioregs;
im = (immap_t *) CONFIG_SYS_IMMR;
gpioregs = &im->gpio;
out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
/*
* out_be32(&gpioregs->gpdir, 0xC2293020);
* workaround for a hardware effect: configure direction in pieces,
* setting all outputs at once drops the reset line too low and
* makes us lose the MII connection (breaks ethernet for us)
*/
out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
udelay(10);
setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
udelay(10);
setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
udelay(10);
setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
/* to turn from red to yellow when U-Boot runs */
setbits_be32(&gpioregs->gpdat, 0x00002020);
out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
}
/* the physical location of the pins */
#define GPIOKEY_ROW_BITMASK 0x40000000
#define GPIOKEY_ROW_UPPER 0
#define GPIOKEY_ROW_LOWER 1
#define GPIOKEY_COL0_BITMASK 0x20000000
#define GPIOKEY_COL1_BITMASK 0x10000000
#define GPIOKEY_COL2_BITMASK 0x08000000
/* the logical presentation of pressed keys */
#define GPIOKEY_BIT_FNLEFT (1 << 5)
#define GPIOKEY_BIT_FNRIGHT (1 << 4)
#define GPIOKEY_BIT_DIRUP (1 << 3)
#define GPIOKEY_BIT_DIRLEFT (1 << 2)
#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
#define GPIOKEY_BIT_DIRDOWN (1 << 0)
/* the hotkey combination which starts recovery */
#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
GPIOKEY_BIT_DIRDOWN)
static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
{
if (row)
setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
else
clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
udelay(10);
}
static u32 gpio_querykbd(void)
{
immap_t *im;
gpio512x_t *gpioregs;
u32 keybits;
u32 input;
im = (immap_t *)CONFIG_SYS_IMMR;
gpioregs = &im->gpio;
keybits = 0;
/* query upper row */
gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
input = in_be32(&gpioregs->gpdat);
if ((input & GPIOKEY_COL0_BITMASK) == 0)
keybits |= GPIOKEY_BIT_FNLEFT;
if ((input & GPIOKEY_COL1_BITMASK) == 0)
keybits |= GPIOKEY_BIT_DIRUP;
if ((input & GPIOKEY_COL2_BITMASK) == 0)
keybits |= GPIOKEY_BIT_FNRIGHT;
/* query lower row */
gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
input = in_be32(&gpioregs->gpdat);
if ((input & GPIOKEY_COL0_BITMASK) == 0)
keybits |= GPIOKEY_BIT_DIRLEFT;
if ((input & GPIOKEY_COL1_BITMASK) == 0)
keybits |= GPIOKEY_BIT_DIRRIGHT;
if ((input & GPIOKEY_COL2_BITMASK) == 0)
keybits |= GPIOKEY_BIT_DIRDOWN;
/* return bit pattern for keys */
return keybits;
}
/* excerpt from the recovery's hw_info.h */
struct __attribute__ ((__packed__)) eeprom_layout {
char magic[3]; /** 'ifm' */
u8 len[2]; /** content length without magic/len fields */
u8 version[3]; /** structure version */
u8 type; /** type of PCB */
u8 reserved[0x37]; /** padding up to offset 0x40 */
u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
};
#define HW_COMP_MAINCPU 2
static struct eeprom_layout eeprom_content;
static int eeprom_is_valid;
static int eeprom_version;
#define get_eeprom_field_int(name) ({ \
int value; \
int idx; \
value = 0; \
for (idx = 0; idx < sizeof(name); idx++) { \
value <<= 8; \
value |= name[idx]; \
} \
value; \
})
static int read_eeprom(void)
{
return -ENOSYS;
}
int mac_read_from_eeprom(void)
{
const u8 *mac;
const char *mac_txt;
if (read_eeprom()) {
printf("I2C EEPROM read failed.\n");
return -1;
}
if (!eeprom_is_valid) {
printf("I2C EEPROM content not valid\n");
return -1;
}
mac = NULL;
switch (eeprom_version) {
case 1:
case 2:
mac = (const u8 *)&eeprom_content.macaddress;
break;
}
if (mac && is_valid_ethaddr(mac)) {
eth_setenv_enetaddr("ethaddr", mac);
if (mac_diag) {
mac_txt = getenv("ethaddr");
if (mac_txt)
printf("DIAG: MAC value [%s]\n", mac_txt);
else
printf("DIAG: failed to setup MAC env\n");
}
}
return 0;
}
/*
* BEWARE!
* this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
* which the ADS, Aria or PDM360NG boards are using
* (the steps outlined here refer to the Micron datasheet)
*/
u32 sdram_init_seq[] = {
/* item 6, at least one NOP after CKE went high */
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
/* item 7, precharge all; item 8, tRP (20ns) */
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP,
/* item 9, extended mode register; item 10, tMRD 10ns) */
CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
CONFIG_SYS_DDRCMD_NOP,
/*
* item 11, (base) mode register _with_ reset DLL;
* item 12, tMRD (10ns)
*/
CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
CONFIG_SYS_MICRON_BMODE_PARAM,
CONFIG_SYS_DDRCMD_NOP,
/* item 13, precharge all; item 14, tRP (20ns) */
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP,
/*
* item 15, auto refresh (i.e. refresh with CKE held high);
* item 16, tRFC (70ns)
*/
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
/*
* item 17, auto refresh (i.e. refresh with CKE held high);
* item 18, tRFC (70ns)
*/
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
CONFIG_SYS_DDRCMD_NOP,
/*
* item 21, "actually done", but make sure 200 DRAM clock cycles
* have passed after DLL reset before READ requests are issued
* (200 cycles at 160MHz -> 1.25 usec)
*/
/* EMPTY, optional, we don't do it */
};
int dram_init(void)
{
gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
ARRAY_SIZE(sdram_init_seq));
return 0;
}
int misc_init_r(void)
{
u32 keys;
char *s;
int want_recovery;
/* setup GPIO directions and initial values */
gpio_configure();
/*
* enforce the start of the recovery system when
* - the appropriate keys were pressed
* - "some" external software told us to
* - a previous installation was aborted or has failed
*/
want_recovery = 0;
keys = gpio_querykbd();
if (gpio_diag)
printf("GPIO keyboard status [0x%02X]\n", keys);
if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
printf("detected recovery request (keyboard)\n");
want_recovery = 1;
}
s = getenv("want_recovery");
if ((s != NULL) && (*s != '\0')) {
printf("detected recovery request (environment)\n");
want_recovery = 1;
}
s = getenv("install_in_progress");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation has not completed\n");
want_recovery = 1;
}
s = getenv("install_failed");
if ((s != NULL) && (*s != '\0')) {
printf("previous installation has failed\n");
want_recovery = 1;
}
if (want_recovery) {
printf("enforced start of the recovery system\n");
setenv("bootcmd", "run recovery");
}
/*
* boot the recovery system without waiting; boot the
* production system without waiting by default, only
* insert a pause (to provide a chance to get a prompt)
* when GPIO keys were pressed during power on
*/
if (want_recovery)
setenv("bootdelay", "0");
else if (!keys)
setenv("bootdelay", "0");
else
setenv("bootdelay", "2");
/* get the ethernet MAC from I2C EEPROM */
mac_read_from_eeprom();
return 0;
}
/* setup specific IO pad configuration */
static iopin_t ioregs_init[] = {
{ /* LPC CS3 */
offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
{ /* LPC CS1 */
offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* LPC CS2 */
offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* LPC CS4, CS5 */
offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
{ /* SDHC CLK, CMD, D0, D1, D2, D3 */
offsetof(struct ioctrl512x, io_control_pata_ior), 6,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
{ /* GPIO keyboard */
offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO DN1 PF, LCD power, DN2 PF */
offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO reset AS-i */
offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO reset safety */
offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO reset netX */
offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO ma2 en */
offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO SD CD, SD WP */
offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* FEC RX DV */
offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(2),
},
{ /* GPIO AS-i prog, AS-i done, LCD backlight */
offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO AS-i wdg */
offsetof(struct ioctrl512x, io_control_pci_req2), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO safety wdg */
offsetof(struct ioctrl512x, io_control_pci_req1), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO netX wdg */
offsetof(struct ioctrl512x, io_control_pci_req0), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO IRQ powerfail */
offsetof(struct ioctrl512x, io_control_pci_inta), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO AS-i PWRD */
offsetof(struct ioctrl512x, io_control_pci_frame), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO LED0, LED1 */
offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /* DIU clk */
offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(2),
},
{ /* FEC TX ER, CRS */
offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
{ /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
offsetof(struct ioctrl512x, io_control_irq0), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
{ /*
* FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
* rdx 3-0, mdio, rx clk
*/
offsetof(struct ioctrl512x, io_control_psc0_0), 15,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
/* optional: make sure PSC3 remains the serial console */
{ /* LPC CS6 */
offsetof(struct ioctrl512x, io_control_psc3_4), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
/* make sure PSC4 remains available for SPI,
*BUT* PSC4_1 is a GPIO kind of SS! */
{ /* enforce drive strength on the SPI pin */
offsetof(struct ioctrl512x, io_control_psc4_0), 5,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{
offsetof(struct ioctrl512x, io_control_psc4_1), 1,
IO_PIN_OVER_FMUX,
IO_PIN_FMUX(3),
},
/* optional: make sure PSC5 remains available for SPI */
{ /* enforce drive strength on the SPI pin */
offsetof(struct ioctrl512x, io_control_psc5_0), 5,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(1),
},
{ /* LPC TSIZ1 */
offsetof(struct ioctrl512x, io_control_psc6_0), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(1) | IO_PIN_DS(2),
},
{ /* DIU hsync */
offsetof(struct ioctrl512x, io_control_psc6_1), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(1),
},
{ /* DIU vsync */
offsetof(struct ioctrl512x, io_control_psc6_4), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(1),
},
{ /* PSC7, part of DIU RGB */
offsetof(struct ioctrl512x, io_control_psc7_0), 2,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(1),
},
{ /* PSC7, safety UART */
offsetof(struct ioctrl512x, io_control_psc7_2), 2,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(0) | IO_PIN_DS(1),
},
{ /* DIU (part of) RGB[] */
offsetof(struct ioctrl512x, io_control_psc8_3), 16,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(1),
},
{ /* DIU data enable */
offsetof(struct ioctrl512x, io_control_psc11_4), 1,
IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
IO_PIN_FMUX(2) | IO_PIN_DS(1),
},
/* reduce LPB drive strength for improved EMI */
{ /* LPC OE, LPC RW */
offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* LPC AX03 through LPC AD00 */
offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* LPC CS5 */
offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* SDHC CLK */
offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
{ /* SDHC DATA */
offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
IO_PIN_OVER_DRVSTR,
IO_PIN_DS(2),
},
};
int checkboard(void)
{
puts("Board: ifm AC14xx\n");
/* initialize function mux & slew rate IO inter alia on IO Pins */
iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

77
board/ifm/o2dnt2/Kconfig
View File

@ -1,77 +0,0 @@
if TARGET_O2D
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o2d"
endif
if TARGET_O2D300
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o2d300"
endif
if TARGET_O2DNT2
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o2dnt2"
endif
if TARGET_O2I
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o2i"
endif
if TARGET_O2MNT
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o2mnt"
endif
if TARGET_O3DNT
config SYS_BOARD
default "o2dnt2"
config SYS_VENDOR
default "ifm"
config SYS_CONFIG_NAME
default "o3dnt"
endif

20
board/ifm/o2dnt2/MAINTAINERS
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O2DNT2 BOARD
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
F: board/ifm/o2dnt2/
F: include/configs/o2d.h
F: configs/O2D_defconfig
F: include/configs/o2d300.h
F: configs/O2D300_defconfig
F: include/configs/o2dnt2.h
F: configs/O2DNT2_defconfig
F: configs/O2DNT2_RAMBOOT_defconfig
F: include/configs/o2i.h
F: configs/O2I_defconfig
F: include/configs/o2mnt.h
F: configs/O2MNT_defconfig
F: configs/O2MNT_O2M110_defconfig
F: configs/O2MNT_O2M112_defconfig
F: configs/O2MNT_O2M113_defconfig
F: include/configs/o3dnt.h
F: configs/O3DNT_defconfig

8
board/ifm/o2dnt2/Makefile
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#
# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := o2dnt2.o

388
board/ifm/o2dnt2/o2dnt2.c
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/*
* Partially derived from board code for digsyMTC,
* (C) Copyright 2009
* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc5xxx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <miiphy.h>
#include <net.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
enum ifm_sensor_type {
O2DNT = 0x00, /* !< O2DNT 32MB */
O2DNT2 = 0x01, /* !< O2DNT2 64MB */
O3DNT = 0x02, /* !< O3DNT 32MB */
O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
UNKNOWN = 0xff, /* !< Unknow sensor */
};
static enum ifm_sensor_type gt_ifm_sensor_type;
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
long control = SDRAM_CONTROL | hi_addr_bit;
/* unlock mode register */
out_be32(&sdram->ctrl, control | 0x80000000);
/* precharge all banks */
out_be32(&sdram->ctrl, control | 0x80000002);
/* auto refresh */
out_be32(&sdram->ctrl, control | 0x80000004);
/* set mode register */
out_be32(&sdram->mode, SDRAM_MODE);
/* normal operation */
out_be32(&sdram->ctrl, control);
}
#endif
/*
* ATTENTION: Although partially referenced dram_init does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
int dram_init(void)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
if (gt_ifm_sensor_type == O2DNT2) {
/* activate SDRAM CS1 */
setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
}
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
/* setup config registers */
out_be32(&sdram->config1, SDRAM_CONFIG1);
out_be32(&sdram->config2, SDRAM_CONFIG2);
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
out_be32(&mmap_ctl->sdram0,
(0x13 + __builtin_ffs(dramsize >> 20) - 1));
} else {
out_be32(&mmap_ctl->sdram0, 0); /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20))
dramsize2 = 0;
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
out_be32(&mmap_ctl->sdram1, (dramsize |
(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
} else {
out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32(&sdram->sdelay, 0x04);
gd->ram_size = dramsize + dramsize2;
return 0;
}
#define GPT_GPIO_IN 0x4
int checkboard(void)
{
struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
unsigned char board_config = 0;
int i;
/* switch gpt0 - gpt7 to input */
for (i = 0; i < 7; i++)
out_be32(&gpt[i].emsr, GPT_GPIO_IN);
/* get configuration byte on timer-port */
for (i = 0; i < 7; i++)
board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
puts("Board: ");
switch (board_config) {
case 0:
puts("O2DNT\n");
gt_ifm_sensor_type = O2DNT;
break;
case 1:
puts("O3DNT\n");
gt_ifm_sensor_type = O3DNT;
break;
case 2:
puts("O2DNT2\n");
gt_ifm_sensor_type = O2DNT2;
break;
case 64:
puts("O3DNT Minerva\n");
gt_ifm_sensor_type = O3DNT_MIN;
break;
default:
puts("Unknown\n");
gt_ifm_sensor_type = UNKNOWN;
break;
}
return 0;
}
int board_early_init_r(void)
{
struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in flash.
*/
clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
/* disable CS_BOOT */
clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
/* enable CS0 */
setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
return 0;
}
#define MIIM_LXT971_LED_CFG_REG 0x14
#define LXT971_LED_CFG_LINK_STATUS 0x4000
#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
#define LXT971_LED_CFG_PULSE_STRETCH 0x0002
/*
* Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
*/
void reset_phy(void)
{
/*
* Set LED configuration bits.
* It can't be done in misc_init_r() since FEC is not
* initialized at this time. Therefore we do it here.
*/
miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
LXT971_LED_CFG_LINK_STATUS |
LXT971_LED_CFG_RX_TX_ACTIVITY |
LXT971_LED_CFG_LINK_ACTIVITY |
LXT971_LED_CFG_PULSE_STRETCH);
}
#if defined(CONFIG_POST)
/*
* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
* is left open, no keypress is detected.
*/
int post_hotkeys_pressed(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
/*
* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
* CODEC or UART mode. Consumer IrDA should still be possible.
*/
clrbits_be32(&gpio->port_config, 0x07000000);
setbits_be32(&gpio->port_config, 0x03000000);
/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
setbits_be32(&gpio->simple_gpioe, 0x20000000);
/* Configure GPIO_IRDA_1 as input */
clrbits_be32(&gpio->simple_ddr, 0x20000000);
return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
}
#endif
#ifdef CONFIG_PCI
static struct pci_controller hose;
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
flash_info_t *dev = &flash_info[0];
int off;
struct fdt_property *prop;
int len;
u32 *reg, *reg2;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
if (off < 0) {
printf("Could not find fsl,mpc5200b-lpb node.\n");
return;
}
/* found compatible property */
prop = fdt_get_property_w(blob, off, "ranges", &len);
if (prop) {
reg = reg2 = (u32 *)&prop->data[0];
reg[2] = dev->start[0];
reg[3] = dev->size;
fdt_setprop(blob, off, "ranges", reg2, len);
} else
printf("Could not find ranges\n");
}
extern ulong flash_get_size(phys_addr_t base, int banknum);
/* Update the flash baseaddr settings */
int update_flash_size(int flash_size)
{
struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
flash_info_t *dev;
int i;
int size = 0;
unsigned long base = 0x0;
u32 *cs_reg = (u32 *)&mm->cs0_start;
for (i = 0; i < 2; i++) {
dev = &flash_info[i];
if (dev->size) {
/* calculate new base addr for this chipselect */
base -= dev->size;
out_be32(cs_reg, START_REG(base));
cs_reg++;
out_be32(cs_reg, STOP_REG(base, dev->size));
cs_reg++;
/* recalculate the sectoraddr in the cfi driver */
size += flash_get_size(base, i);
}
}
flash_protect_default();
gd->bd->bi_flashstart = base;
return 0;
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
int ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
ft_cpu_setup(blob, bd);
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/* Update reg property in all nor flash nodes too */
fdt_fixup_nor_flash_size(blob);
#endif
ft_adapt_flash_base(blob);
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

9
board/inka4x0/Kconfig
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if TARGET_INKA4X0
config SYS_BOARD
default "inka4x0"
config SYS_CONFIG_NAME
default "inka4x0"
endif

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