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tqm85xx: Update PCI code

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Update to use the recent, common FSL PCI initialization code.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: sr@denx.de
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Peter Tyser 2010-09-29 13:37:28 -05:00 committed by Kumar Gala
parent 4e339b83e9
commit 06412756e7
4 changed files with 58 additions and 125 deletions
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4
board/tqc/tqm85xx/law.c
View File

@ -71,7 +71,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
@ -79,7 +79,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
#ifdef CONFIG_PCIE1
SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
#endif /* CONFIG_PCIE */
};

10
board/tqc/tqm85xx/tlb.c
View File

@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
@ -155,7 +155,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
@ -205,7 +205,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */

149
board/tqc/tqm85xx/tqm85xx.c
View File

@ -38,6 +38,7 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
@ -534,7 +535,6 @@ void local_bus_init (void)
/*
* Initialize PCI Devices, report devices found.
*/
static int first_free_busno;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
@ -544,144 +544,77 @@ static struct pci_controller pci1_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
static inline void init_pci1(void)
void pci_init_board (void)
{
struct fsl_pci_info pci_info[2];
int first_free_busno = 0;
int num = 0;
int pcie_ep;
__maybe_unused int pcie_configured;
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
u32 pordevsr = in_be32(&gur->pordevsr);
__maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
#ifdef CONFIG_PCI1
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
/* PORDEVSR[15] */
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
/* PORDEVSR[14] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
/* PORPLLSR[16] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR);
uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333333) ? "33" :
(pci_speed == 66666666) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
/* outbound memory */
pci_set_region (r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region (r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
printf (" PCI on bus %02x..%02x\n",
hose->first_busno, hose->last_busno);
first_free_busno = hose->last_busno + 1;
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
#ifdef CONFIG_PCIX_CHECK
if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
ushort reg16 =
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
uint dev = PCI_BDF(hose->first_busno, 0, 0);
uint dev = PCI_BDF(0, 0, 0);
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
puts ("PCI-X will only work at 66 MHz\n");
pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
reg16);
pci_write_config_word(dev, PCIX_COMMAND, reg16);
}
#endif
} else {
puts ("PCI1: disabled\n");
printf(" PCI1: disabled\n");
}
#else /* !CONFIG_PCI1 */
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif /* CONFIG_PCI1 */
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
static inline void init_pcie1(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep;
struct pci_region *r = hose->regions;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR);
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("PCIe: %s, base address %x",
pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (", with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
puts ("\n");
/* outbound memory */
pci_set_region (r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region (r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
printf (" PCIe on bus %02x..%02x\n",
hose->first_busno, hose->last_busno);
first_free_busno = hose->last_busno + 1;
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected as %s\n",
pcie_ep ? "Endpoint" : "Root Complex");
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf ("PCIe: disabled\n");
printf(" PCIE1: disabled\n");
}
#else /* !CONFIG_PCIE1 */
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
#endif /* CONFIG_PCIE1 */
}
void pci_init_board (void)
{
init_pci1();
init_pcie1();
}
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{

20
include/configs/TQM85xx.h
View File

@ -380,11 +380,11 @@
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCIE1
@ -393,16 +393,16 @@
* Addresses are mapped 1-1.
*/
#ifdef CONFIG_TQM_BIGFLASH
#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
#else /* !CONFIG_TQM_BIGFLASH */
#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
#endif /* CONFIG_TQM_BIGFLASH */
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
#endif /* CONFIG_PCIE1 */