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85xx: Improve MPIC initialization

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The MPIC initialization code for Freescale e500 CPUs was not using I/O
accessors, and it was not issuing a read-back to the MPIC after setting
mixed mode.  This may be the cause of a spurious interrupt on some systems.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi 2009-08-20 17:41:11 -05:00 committed by Kumar Gala
parent c17b79fbd0
commit 05f6f66474
1 changed files with 7 additions and 5 deletions
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12
cpu/mpc85xx/interrupts.c
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@ -31,15 +31,17 @@
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
int interrupt_init_cpu(unsigned long *decrementer_count)
int interrupt_init_cpu(unsigned int *decrementer_count)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR;
pic->gcr = MPC85xx_PICGCR_RST;
while (pic->gcr & MPC85xx_PICGCR_RST)
out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
;
pic->gcr = MPC85xx_PICGCR_M;
out_be32(&pic->gcr, MPC85xx_PICGCR_M);
in_be32(&pic->gcr);
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;