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Merge tag 'u-boot-rockchip-20220905' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

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- migrate to use binman for U-Boot image generate on rockchip platform;
- Some fixes for rk3399 and rk3308;
This commit is contained in:
Tom Rini
2022-09-04 22:35:40 -04:00
parent 427aa3c9b7 f103c11266
commit 05f135ab3e
24 changed files with 313 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@@ -1974,7 +1974,7 @@ config ARCH_STM32MP
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select BLK
select BINMAN if SPL_OPTEE || (SPL && !ARM64)
select BINMAN if SPL_OPTEE || SPL
select DM
select DM_GPIO
select DM_I2C

2
arch/arm/dts/px30-u-boot.dtsi
View File

@@ -3,6 +3,8 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &emmc;

2
arch/arm/dts/rk3288-u-boot.dtsi
View File

@@ -56,7 +56,7 @@
};
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";

16
arch/arm/dts/rk3288.dtsi
View File

@@ -109,48 +109,48 @@
ports = <&vopl_out>, <&vopb_out>;
};
sdmmc: dwmmc@ff0c0000 {
sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0c0000 0x4000>;
status = "disabled";
};
sdio0: dwmmc@ff0d0000 {
sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0d0000 0x4000>;
status = "disabled";
};
sdio1: dwmmc@ff0e0000 {
sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0e0000 0x4000>;
status = "disabled";
};
emmc: dwmmc@ff0f0000 {
emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0f0000 0x4000>;

2
arch/arm/dts/rk3308-u-boot.dtsi
View File

@@ -3,6 +3,8 @@
*(C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &emmc;

2
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
View File

@@ -3,6 +3,8 @@
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
#include "rockchip-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &sdmmc;

2
arch/arm/dts/rk3328-u-boot.dtsi
View File

@@ -3,6 +3,8 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &emmc;

1
arch/arm/dts/rk3368-u-boot.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include <dt-bindings/memory/rk3368-dmc.h>
#include "rockchip-u-boot.dtsi"
/ {
dmc: dmc@ff610000 {

2
arch/arm/dts/rk3399-u-boot.dtsi
View File

@@ -60,7 +60,7 @@
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";

2
arch/arm/dts/rk3568-u-boot.dtsi
View File

@@ -3,6 +3,8 @@
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include "rockchip-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdhci;

46
arch/arm/dts/rockchip-u-boot.dtsi
View File

@@ -17,13 +17,57 @@
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
blob {
mkimage {
filename = "idbloader.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
#ifdef CONFIG_TPL
multiple-data-files;
u-boot-tpl {
};
#endif
u-boot-spl {
};
};
#ifdef CONFIG_ARM64
blob {
filename = "u-boot.itb";
#else
u-boot-img {
#endif
offset = <CONFIG_SPL_PAD_TO>;
};
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
filename = "u-boot-rockchip-spi.bin";
pad-byte = <0xff>;
mkimage {
filename = "idbloader-spi.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
#ifdef CONFIG_TPL
multiple-data-files;
u-boot-tpl {
};
#endif
u-boot-spl {
};
};
#ifdef CONFIG_ARM64
blob {
filename = "u-boot.itb";
#else
u-boot-img {
#endif
/* Sync with u-boot,spl-payload-offset if present */
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
};
};
#endif
};
#endif

6
arch/arm/mach-rockchip/Kconfig
View File

@@ -425,12 +425,10 @@ config SPL_MMC
config ROCKCHIP_SPI_IMAGE
bool "Build a SPI image for rockchip"
depends on HAS_ROM
help
Some Rockchip SoCs support booting from SPI flash. Enable this
option to produce a 4MB SPI-flash image (called u-boot.rom)
containing U-Boot. The image is built by binman. U-Boot sits near
the start of the image.
option to produce a SPI-flash image containing U-Boot. The image
is built by binman. U-Boot sits near the start of the image.
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default SYS_TEXT_BASE

6
arch/arm/mach-rockchip/rk3308/rk3308.c
View File

@@ -8,6 +8,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/gpio.h>
#include <debug_uart.h>
@@ -142,6 +143,11 @@ enum {
#define GPIO0_A4 4
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
[BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
};
int rk_board_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;

8
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe330000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
};
@@ -180,9 +180,9 @@ const char *spl_decode_boot_device(u32 boot_device)
u32 boot_device;
const char *ofpath;
} spl_boot_devices_tbl[] = {
{ BOOT_DEVICE_MMC1, "/mmc@fe320000" },
{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
{ BOOT_DEVICE_MMC2, "/mmc@fe320000" },
{ BOOT_DEVICE_MMC1, "/mmc@fe330000" },
{ BOOT_DEVICE_SPI, "/spi@ff1d0000/flash@0" },
};
for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)