imx8mm: Sync device tree with linux-next 20220711
Sync imx8mm.dtsi device tree with linux-next 20220711. The main motivation for doing this sync is the sha256 regression reported by Andrey Zhizhikin [1]. The linux-next kernel has the following commit, which disables the job ring 0 and fixes the problem: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20220715&id=dc9c1ceb555ff661e6fc1081434600771f29657c [1] https://lore.kernel.org/u-boot/AM6PR06MB46912207D9460CD9924F35DAA68B9@AM6PR06MB4691.eurprd06.prod.outlook.com/T/#t Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
4ae1fa338b
commit
05996f350d
@ -4,11 +4,11 @@
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*/
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx8mm-pinfunc.h"
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@ -65,6 +65,12 @@
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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nvmem-cells = <&cpu_speed_grade>;
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@ -80,6 +86,12 @@
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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@ -93,6 +105,12 @@
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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@ -106,6 +124,12 @@
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clk IMX8MM_CLK_ARM>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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@ -114,6 +138,10 @@
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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@ -184,7 +212,7 @@
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext4";
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};
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@ -194,10 +222,9 @@
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
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};
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timer {
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@ -260,11 +287,14 @@
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clock-names = "main_clk";
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};
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soc@0 {
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compatible = "simple-bus";
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soc: soc@0 {
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compatible = "fsl,imx8mm-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x3e000000>;
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dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
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nvmem-cells = <&imx8mm_uid>;
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nvmem-cell-names = "soc_unique_id";
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aips1: bus@30000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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@ -273,117 +303,125 @@
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#size-cells = <1>;
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ranges = <0x30000000 0x30000000 0x400000>;
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sai1: sai@30010000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30010000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
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<&clk IMX8MM_CLK_SAI1_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spba2: spba-bus@30000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x30000000 0x100000>;
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ranges;
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sai2: sai@30020000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30020000 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
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<&clk IMX8MM_CLK_SAI2_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai1: sai@30010000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30010000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
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<&clk IMX8MM_CLK_SAI1_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai3: sai@30030000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30030000 0x10000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
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<&clk IMX8MM_CLK_SAI3_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai2: sai@30020000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30020000 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
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<&clk IMX8MM_CLK_SAI2_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai5: sai@30050000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30050000 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
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<&clk IMX8MM_CLK_SAI5_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai3: sai@30030000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30030000 0x10000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
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<&clk IMX8MM_CLK_SAI3_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai6: sai@30060000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30060000 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
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<&clk IMX8MM_CLK_SAI6_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai5: sai@30050000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30050000 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
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<&clk IMX8MM_CLK_SAI5_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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micfil: audio-controller@30080000 {
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compatible = "fsl,imx8mm-micfil";
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reg = <0x30080000 0x10000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_PDM_IPG>,
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<&clk IMX8MM_CLK_PDM_ROOT>,
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<&clk IMX8MM_AUDIO_PLL1_OUT>,
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<&clk IMX8MM_AUDIO_PLL2_OUT>,
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<&clk IMX8MM_CLK_EXT3>;
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clock-names = "ipg_clk", "ipg_clk_app",
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"pll8k", "pll11k", "clkext3";
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dmas = <&sdma2 24 25 0x80000000>;
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dma-names = "rx";
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status = "disabled";
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};
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sai6: sai@30060000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
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reg = <0x30060000 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
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<&clk IMX8MM_CLK_SAI6_ROOT>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spdif1: spdif@30090000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x30090000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
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<&clk IMX8MM_CLK_24M>, /* rxtx0 */
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<&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
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<&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
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<&clk IMX8MM_CLK_DUMMY>; /* spba */
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7", "spba";
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dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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micfil: audio-controller@30080000 {
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compatible = "fsl,imx8mm-micfil";
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reg = <0x30080000 0x10000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_PDM_IPG>,
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<&clk IMX8MM_CLK_PDM_ROOT>,
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<&clk IMX8MM_AUDIO_PLL1_OUT>,
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<&clk IMX8MM_AUDIO_PLL2_OUT>,
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<&clk IMX8MM_CLK_EXT3>;
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clock-names = "ipg_clk", "ipg_clk_app",
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"pll8k", "pll11k", "clkext3";
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dmas = <&sdma2 24 25 0x80000000>;
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dma-names = "rx";
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status = "disabled";
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};
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spdif1: spdif@30090000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x30090000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
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<&clk IMX8MM_CLK_24M>, /* rxtx0 */
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<&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
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<&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
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<&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
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<&clk IMX8MM_CLK_DUMMY>; /* spba */
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7", "spba";
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dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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};
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gpio1: gpio@30200000 {
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@ -522,9 +560,17 @@
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#address-cells = <1>;
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#size-cells = <1>;
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imx8mm_uid: unique-id@410 {
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reg = <0x4 0x8>;
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};
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cpu_speed_grade: speed-grade@10 {
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reg = <0x10 4>;
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};
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fec_mac_address: mac-address@90 {
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reg = <0x90 6>;
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};
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};
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anatop: anatop@30360000 {
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@ -556,6 +602,11 @@
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wakeup-source;
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status = "disabled";
|
||||
};
|
||||
|
||||
snvs_lpgpr: snvs-lpgpr {
|
||||
compatible = "fsl,imx8mm-snvs-lpgpr",
|
||||
"fsl,imx7d-snvs-lpgpr";
|
||||
};
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
@ -573,8 +624,7 @@
|
||||
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
|
||||
<&clk IMX8MM_SYS_PLL3>,
|
||||
<&clk IMX8MM_VIDEO_PLL1>,
|
||||
<&clk IMX8MM_AUDIO_PLL1>,
|
||||
<&clk IMX8MM_AUDIO_PLL2>;
|
||||
<&clk IMX8MM_AUDIO_PLL1>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
|
||||
<&clk IMX8MM_ARM_PLL_OUT>,
|
||||
<&clk IMX8MM_SYS_PLL3_OUT>,
|
||||
@ -584,8 +634,7 @@
|
||||
<400000000>,
|
||||
<750000000>,
|
||||
<594000000>,
|
||||
<393216000>,
|
||||
<361267200>;
|
||||
<393216000>;
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
@ -598,6 +647,7 @@
|
||||
gpc: gpc@303a0000 {
|
||||
compatible = "fsl,imx8mm-gpc";
|
||||
reg = <0x303a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
@ -610,12 +660,15 @@
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
|
||||
clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
|
||||
};
|
||||
|
||||
pgc_pcie: power-domain@1 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_PCIE>;
|
||||
power-domains = <&pgc_hsiomix>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
|
||||
};
|
||||
|
||||
pgc_otg1: power-domain@2 {
|
||||
@ -634,32 +687,63 @@
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
|
||||
clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU_AHB>;
|
||||
<&clk IMX8MM_CLK_GPU_AHB>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
|
||||
<&clk IMX8MM_CLK_GPU_AHB>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
|
||||
<&clk IMX8MM_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <800000000>, <400000000>;
|
||||
};
|
||||
|
||||
pgc_gpu: power-domain@5 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_GPU>;
|
||||
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
||||
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU2D_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU3D_ROOT>;
|
||||
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU2D_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU3D_ROOT>;
|
||||
resets = <&src IMX8MQ_RESET_GPU_RESET>;
|
||||
power-domains = <&pgc_gpumix>;
|
||||
};
|
||||
|
||||
dispmix_pd: power-domain@10 {
|
||||
pgc_vpumix: power-domain@6 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
|
||||
clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_APB_ROOT>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
|
||||
clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
|
||||
};
|
||||
|
||||
mipi_pd: power-domain@11 {
|
||||
pgc_vpu_g1: power-domain@7 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
|
||||
};
|
||||
|
||||
pgc_vpu_g2: power-domain@8 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
|
||||
};
|
||||
|
||||
pgc_vpu_h1: power-domain@9 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
|
||||
};
|
||||
|
||||
pgc_dispmix: power-domain@10 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
|
||||
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
|
||||
<&clk IMX8MM_CLK_DISP_APB>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
|
||||
<&clk IMX8MM_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <500000000>, <200000000>;
|
||||
};
|
||||
|
||||
pgc_mipi: power-domain@11 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MM_POWER_DOMAIN_MIPI>;
|
||||
power-domains = <&dispmix_pd>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -679,7 +763,7 @@
|
||||
clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
|
||||
<&clk IMX8MM_CLK_PWM1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -690,7 +774,7 @@
|
||||
clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
|
||||
<&clk IMX8MM_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -701,7 +785,7 @@
|
||||
clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
|
||||
<&clk IMX8MM_CLK_PWM3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -712,7 +796,7 @@
|
||||
clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
|
||||
<&clk IMX8MM_CLK_PWM4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -733,80 +817,88 @@
|
||||
ranges = <0x30800000 0x30800000 0x400000>,
|
||||
<0x8000000 0x8000000 0x10000000>;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
spba1: spba-bus@30800000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
#size-cells = <1>;
|
||||
reg = <0x30800000 0x100000>;
|
||||
ranges;
|
||||
|
||||
ecspi2: spi@30830000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: spi@30840000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
ecspi2: spi@30830000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
ecspi3: spi@30840000 {
|
||||
compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
|
||||
<&clk IMX8MM_CLK_ECSPI3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MM_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
crypto: crypto@30900000 {
|
||||
@ -824,6 +916,7 @@
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
@ -908,7 +1001,7 @@
|
||||
<&clk IMX8MM_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -922,7 +1015,7 @@
|
||||
<&clk IMX8MM_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -936,7 +1029,7 @@
|
||||
<&clk IMX8MM_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -950,7 +1043,7 @@
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MM_CLK_QSPI_ROOT>;
|
||||
clock-names = "fspi", "fspi_en";
|
||||
clock-names = "fspi_en", "fspi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -966,7 +1059,7 @@
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
|
||||
compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -982,13 +1075,17 @@
|
||||
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
|
||||
<&clk IMX8MM_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MM_CLK_ENET_REF>,
|
||||
<&clk IMX8MM_CLK_ENET_TIMER>;
|
||||
<&clk IMX8MM_CLK_ENET_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
|
||||
<&clk IMX8MM_SYS_PLL2_100M>,
|
||||
<&clk IMX8MM_SYS_PLL2_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
<&clk IMX8MM_SYS_PLL2_125M>,
|
||||
<&clk IMX8MM_SYS_PLL2_50M>;
|
||||
assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
nvmem-cells = <&fec_mac_address>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
fsl,stop-mode = <&gpr 0x10 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1001,6 +1098,84 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0x32c00000 0x32c00000 0x400000>;
|
||||
|
||||
csi: csi@32e20000 {
|
||||
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
|
||||
reg = <0x32e20000 0x1000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
|
||||
clock-names = "mclk";
|
||||
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
csi_in: endpoint {
|
||||
remote-endpoint = <&imx8mm_mipi_csi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
disp_blk_ctrl: blk-ctrl@32e28000 {
|
||||
compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
|
||||
reg = <0x32e28000 0x100>;
|
||||
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
|
||||
<&pgc_dispmix>, <&pgc_mipi>,
|
||||
<&pgc_mipi>;
|
||||
power-domain-names = "bus", "csi-bridge",
|
||||
"lcdif", "mipi-dsi",
|
||||
"mipi-csi";
|
||||
clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MM_CLK_CSI1_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MM_CLK_DISP_ROOT>,
|
||||
<&clk IMX8MM_CLK_DSI_CORE>,
|
||||
<&clk IMX8MM_CLK_DSI_PHY_REF>,
|
||||
<&clk IMX8MM_CLK_CSI1_CORE>,
|
||||
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
|
||||
clock-names = "csi-bridge-axi","csi-bridge-apb",
|
||||
"csi-bridge-core", "lcdif-axi",
|
||||
"lcdif-apb", "lcdif-pix",
|
||||
"dsi-pclk", "dsi-ref",
|
||||
"csi-aclk", "csi-pclk";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
mipi_csi: mipi-csi@32e30000 {
|
||||
compatible = "fsl,imx8mm-mipi-csi2";
|
||||
reg = <0x32e30000 0x1000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
|
||||
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
|
||||
<&clk IMX8MM_SYS_PLL2_1000M>;
|
||||
clock-frequency = <333000000>;
|
||||
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MM_CLK_CSI1_ROOT>,
|
||||
<&clk IMX8MM_CLK_CSI1_PHY_REF>,
|
||||
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
|
||||
clock-names = "pclk", "wrap", "phy", "axi";
|
||||
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
imx8mm_mipi_csi_out: endpoint {
|
||||
remote-endpoint = <&csi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbotg1: usb@32e40000 {
|
||||
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e40000 0x200>;
|
||||
@ -1116,6 +1291,72 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_3d: gpu@38000000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x38000000 0x8000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
||||
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU3D_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU3D_ROOT>;
|
||||
clock-names = "reg", "bus", "core", "shader";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
|
||||
<&clk IMX8MM_GPU_PLL_OUT>;
|
||||
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
|
||||
assigned-clock-rates = <0>, <1000000000>;
|
||||
power-domains = <&pgc_gpu>;
|
||||
};
|
||||
|
||||
gpu_2d: gpu@38008000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x38008000 0x8000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
|
||||
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MM_CLK_GPU2D_ROOT>;
|
||||
clock-names = "reg", "bus", "core";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
|
||||
<&clk IMX8MM_GPU_PLL_OUT>;
|
||||
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
|
||||
assigned-clock-rates = <0>, <1000000000>;
|
||||
power-domains = <&pgc_gpu>;
|
||||
};
|
||||
|
||||
vpu_g1: video-codec@38300000 {
|
||||
compatible = "nxp,imx8mm-vpu-g1";
|
||||
reg = <0x38300000 0x10000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
|
||||
};
|
||||
|
||||
vpu_g2: video-codec@38310000 {
|
||||
compatible = "nxp,imx8mq-vpu-g2";
|
||||
reg = <0x38310000 0x10000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
|
||||
};
|
||||
|
||||
vpu_blk_ctrl: blk-ctrl@38330000 {
|
||||
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
|
||||
reg = <0x38330000 0x100>;
|
||||
power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
|
||||
<&pgc_vpu_g2>, <&pgc_vpu_h1>;
|
||||
power-domain-names = "bus", "g1", "g2", "h1";
|
||||
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
|
||||
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
|
||||
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
|
||||
clock-names = "g1", "g2", "h1";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
|
||||
<&clk IMX8MM_CLK_VPU_G2>;
|
||||
assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
|
||||
<&clk IMX8MM_VPU_PLL_OUT>;
|
||||
assigned-clock-rates = <600000000>,
|
||||
<600000000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>, /* GIC Dist */
|
||||
|
||||
@ -19,4 +19,13 @@
|
||||
#define IMX8MM_POWER_DOMAIN_DISPMIX 10
|
||||
#define IMX8MM_POWER_DOMAIN_MIPI 11
|
||||
|
||||
#define IMX8MM_VPUBLK_PD_G1 0
|
||||
#define IMX8MM_VPUBLK_PD_G2 1
|
||||
#define IMX8MM_VPUBLK_PD_H1 2
|
||||
|
||||
#define IMX8MM_DISPBLK_PD_CSI_BRIDGE 0
|
||||
#define IMX8MM_DISPBLK_PD_LCDIF 1
|
||||
#define IMX8MM_DISPBLK_PD_MIPI_DSI 2
|
||||
#define IMX8MM_DISPBLK_PD_MIPI_CSI 3
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user