pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This commit is contained in:
Horatiu Vultur
Daniel Schwierzeck
parent
ace9c103df
commit
051de9b3eb
@ -526,6 +526,7 @@ F: configs/mscc*
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F: drivers/gpio/mscc_sgpio.c
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F: drivers/spi/mscc_bb_spi.c
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F: include/configs/vcoreiii.h
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F: drivers/pinctrl/mscc/
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MIPS JZ4780
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M: Ezequiel Garcia <ezequiel@collabora.com>
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@ -20,3 +20,12 @@ config PINCTRL_MSCC_LUTON
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help
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Support pin multiplexing and pin configuration control on
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Microsemi luton SoCs.
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config PINCTRL_MSCC_JR2
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depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
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select PINCTRL_MSCC
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default y
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bool "Microsemi jr2 family pin control driver"
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help
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Support pin multiplexing and pin configuration control on
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Microsemi jr2 SoCs.
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@ -3,3 +3,4 @@
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obj-y += mscc-common.o
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obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
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obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
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obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
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@ -22,16 +22,37 @@
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#include <linux/io.h>
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#include "mscc-common.h"
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#define MSCC_GPIO_OUT_SET 0x0
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#define MSCC_GPIO_OUT_CLR 0x4
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#define MSCC_GPIO_OUT 0x8
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#define MSCC_GPIO_IN 0xc
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#define MSCC_GPIO_OE 0x10
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#define MSCC_GPIO_INTR 0x14
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#define MSCC_GPIO_INTR_ENA 0x18
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#define MSCC_GPIO_INTR_IDENT 0x1c
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#define MSCC_GPIO_ALT0 0x20
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#define MSCC_GPIO_ALT1 0x24
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static void mscc_writel(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(BIT(offset), addr);
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else
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writel(BIT(offset % 32), addr + 4);
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}
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static unsigned int mscc_readl(unsigned int offset, void *addr)
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{
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if (offset < 32)
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return readl(addr);
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else
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return readl(addr + 4);
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}
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static void mscc_setbits(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(readl(addr) | BIT(offset), addr);
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else
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writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
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}
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static void mscc_clrbits(unsigned int offset, void *addr)
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{
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if (offset < 32)
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writel(readl(addr) & ~BIT(offset), addr);
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else
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writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
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}
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static int mscc_get_functions_count(struct udevice *dev)
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{
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@ -67,7 +88,7 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
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{
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struct mscc_pinctrl *info = dev_get_priv(dev);
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struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
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int f;
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int f, offset, regoff;
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f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
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if (f < 0)
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@ -79,15 +100,22 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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*/
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offset = pin->pin;
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regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
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if (offset >= 32) {
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offset = offset % 32;
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regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
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}
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if (f & BIT(0))
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setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
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mscc_setbits(offset, info->regs + regoff);
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else
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clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
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mscc_clrbits(offset, info->regs + regoff);
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if (f & BIT(1))
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setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
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mscc_setbits(offset, info->regs + regoff + 4);
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else
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clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
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mscc_clrbits(offset, info->regs + regoff + 4);
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return 0;
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}
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@ -120,8 +148,8 @@ static int mscc_create_group_func_map(struct udevice *dev,
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}
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info->func[f].ngroups = npins;
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info->func[f].groups = devm_kzalloc(dev, npins *
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sizeof(char *), GFP_KERNEL);
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info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
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GFP_KERNEL);
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if (!info->func[f].groups)
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return -ENOMEM;
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@ -150,9 +178,15 @@ static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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unsigned int val;
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val = readl(info->regs + MSCC_GPIO_IN);
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if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
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BIT(offset % 32))
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val = mscc_readl(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
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else
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val = mscc_readl(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
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return !!(val & BIT(offset));
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return !!(val & BIT(offset % 32));
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}
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static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
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@ -160,9 +194,11 @@ static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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if (value)
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writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
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mscc_writel(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
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else
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writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
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mscc_writel(offset,
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info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
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return 0;
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}
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@ -172,16 +208,16 @@ static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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unsigned int val;
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val = readl(info->regs + MSCC_GPIO_OE);
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val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
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return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
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mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return 0;
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}
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@ -191,7 +227,7 @@ static int mscc_gpio_direction_output(struct udevice *dev,
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{
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struct mscc_pinctrl *info = dev_get_priv(dev->parent);
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setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
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mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
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return mscc_gpio_set(dev, offset, value);
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}
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@ -215,7 +251,8 @@ const struct pinctrl_ops mscc_pinctrl_ops = {
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int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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const struct mscc_pin_data *mscc_pins, int num_pins,
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char *const *function_names)
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char * const *function_names,
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const unsigned long *mscc_gpios)
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{
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struct mscc_pinctrl *priv = dev_get_priv(dev);
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int ret;
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@ -230,6 +267,7 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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priv->mscc_pins = mscc_pins;
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priv->num_pins = num_pins;
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priv->function_names = function_names;
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priv->mscc_gpios = mscc_gpios;
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ret = mscc_pinctrl_register(dev, priv);
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return ret;
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@ -9,6 +9,19 @@
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#define MSCC_FUNC_PER_PIN 4
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enum mscc_regs_gpio {
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MSCC_GPIO_OUT_SET,
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MSCC_GPIO_OUT_CLR,
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MSCC_GPIO_OUT,
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MSCC_GPIO_IN,
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MSCC_GPIO_OE,
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MSCC_GPIO_INTR,
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MSCC_GPIO_INTR_ENA,
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MSCC_GPIO_INTR_IDENT,
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MSCC_GPIO_ALT0,
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MSCC_GPIO_ALT1,
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};
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struct mscc_pin_caps {
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unsigned int pin;
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unsigned char functions[MSCC_FUNC_PER_PIN];
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@ -41,11 +54,13 @@ struct mscc_pinctrl {
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const struct mscc_pin_data *mscc_pins;
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int num_pins;
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char * const *function_names;
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const unsigned long *mscc_gpios;
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};
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int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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const struct mscc_pin_data *mscc_pins, int num_pins,
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char * const *function_names);
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char * const *function_names,
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const unsigned long *mscc_gpios);
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const struct pinctrl_ops mscc_pinctrl_ops;
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const struct dm_gpio_ops mscc_gpio_ops;
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323
drivers/pinctrl/mscc/pinctrl-jr2.c
Normal file
323
drivers/pinctrl/mscc/pinctrl-jr2.c
Normal file
@ -0,0 +1,323 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <horatiu.vultur@microchip.com>
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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#include <asm/system.h>
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#include "mscc-common.h"
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enum {
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FUNC_NONE,
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FUNC_GPIO,
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FUNC_IRQ0_IN,
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FUNC_IRQ0_OUT,
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_MIIM1,
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FUNC_MIIM2,
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FUNC_PCI_WAKE,
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FUNC_PTP0,
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FUNC_PTP1,
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FUNC_PTP2,
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FUNC_PTP3,
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FUNC_PWM,
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FUNC_RECO_CLK0,
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FUNC_RECO_CLK1,
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FUNC_SFP0,
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FUNC_SFP1,
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FUNC_SFP2,
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FUNC_SFP3,
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FUNC_SFP4,
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FUNC_SFP5,
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FUNC_SFP6,
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FUNC_SFP7,
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FUNC_SFP8,
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FUNC_SFP9,
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FUNC_SFP10,
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FUNC_SFP11,
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FUNC_SFP12,
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FUNC_SFP13,
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FUNC_SFP14,
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FUNC_SFP15,
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FUNC_SG0,
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FUNC_SG1,
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FUNC_SG2,
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FUNC_SI,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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FUNC_MAX
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};
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static char * const jr2_function_names[] = {
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[FUNC_NONE] = "none",
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[FUNC_GPIO] = "gpio",
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[FUNC_IRQ0_IN] = "irq0_in",
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[FUNC_IRQ0_OUT] = "irq0_out",
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[FUNC_IRQ1_IN] = "irq1_in",
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[FUNC_IRQ1_OUT] = "irq1_out",
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[FUNC_MIIM1] = "miim1",
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[FUNC_MIIM2] = "miim2",
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[FUNC_PCI_WAKE] = "pci_wake",
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[FUNC_PTP0] = "ptp0",
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[FUNC_PTP1] = "ptp1",
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[FUNC_PTP2] = "ptp2",
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[FUNC_PTP3] = "ptp3",
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[FUNC_PWM] = "pwm",
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[FUNC_RECO_CLK0] = "reco_clk0",
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[FUNC_RECO_CLK1] = "reco_clk1",
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[FUNC_SFP0] = "sfp0",
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[FUNC_SFP1] = "sfp1",
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[FUNC_SFP2] = "sfp2",
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[FUNC_SFP3] = "sfp3",
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[FUNC_SFP4] = "sfp4",
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[FUNC_SFP5] = "sfp5",
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[FUNC_SFP6] = "sfp6",
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[FUNC_SFP7] = "sfp7",
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[FUNC_SFP8] = "sfp8",
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[FUNC_SFP9] = "sfp9",
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[FUNC_SFP10] = "sfp10",
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[FUNC_SFP11] = "sfp11",
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[FUNC_SFP12] = "sfp12",
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[FUNC_SFP13] = "sfp13",
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[FUNC_SFP14] = "sfp14",
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[FUNC_SFP15] = "sfp15",
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[FUNC_SG0] = "sg0",
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[FUNC_SG1] = "sg1",
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[FUNC_SG2] = "sg2",
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[FUNC_SI] = "si",
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[FUNC_TACHO] = "tacho",
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[FUNC_TWI] = "twi",
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[FUNC_TWI2] = "twi2",
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[FUNC_TWI_SCL_M] = "twi_scl_m",
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[FUNC_UART] = "uart",
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[FUNC_UART2] = "uart2",
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};
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#define JR2_P(p, f0, f1) \
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static struct mscc_pin_caps jr2_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
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}, \
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}
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JR2_P(0, SG0, NONE);
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JR2_P(1, SG0, NONE);
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JR2_P(2, SG0, NONE);
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JR2_P(3, SG0, NONE);
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JR2_P(4, SG1, NONE);
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JR2_P(5, SG1, NONE);
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JR2_P(6, IRQ0_IN, IRQ0_OUT);
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JR2_P(7, IRQ1_IN, IRQ1_OUT);
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JR2_P(8, PTP0, NONE);
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JR2_P(9, PTP1, NONE);
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JR2_P(10, UART, NONE);
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JR2_P(11, UART, NONE);
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JR2_P(12, SG1, NONE);
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JR2_P(13, SG1, NONE);
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JR2_P(14, TWI, TWI_SCL_M);
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JR2_P(15, TWI, NONE);
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JR2_P(16, SI, TWI_SCL_M);
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JR2_P(17, SI, TWI_SCL_M);
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JR2_P(18, SI, TWI_SCL_M);
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JR2_P(19, PCI_WAKE, NONE);
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JR2_P(20, IRQ0_OUT, TWI_SCL_M);
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JR2_P(21, IRQ1_OUT, TWI_SCL_M);
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JR2_P(22, TACHO, NONE);
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JR2_P(23, PWM, NONE);
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JR2_P(24, UART2, NONE);
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JR2_P(25, UART2, SI);
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JR2_P(26, PTP2, SI);
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JR2_P(27, PTP3, SI);
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JR2_P(28, TWI2, SI);
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JR2_P(29, TWI, SI);
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JR2_P(30, SG2, SI);
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JR2_P(31, SG2, SI);
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JR2_P(32, SG2, SI);
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JR2_P(33, SG2, SI);
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JR2_P(34, NONE, TWI_SCL_M);
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JR2_P(35, NONE, TWI_SCL_M);
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JR2_P(36, NONE, TWI_SCL_M);
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JR2_P(37, NONE, TWI_SCL_M);
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JR2_P(38, NONE, TWI_SCL_M);
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JR2_P(39, NONE, TWI_SCL_M);
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JR2_P(40, NONE, TWI_SCL_M);
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JR2_P(41, NONE, TWI_SCL_M);
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JR2_P(42, NONE, TWI_SCL_M);
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JR2_P(43, NONE, TWI_SCL_M);
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JR2_P(44, NONE, SFP8);
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JR2_P(45, NONE, SFP9);
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JR2_P(46, NONE, SFP10);
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JR2_P(47, NONE, SFP11);
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JR2_P(48, SFP0, NONE);
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JR2_P(49, SFP1, SI);
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JR2_P(50, SFP2, SI);
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JR2_P(51, SFP3, SI);
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JR2_P(52, SFP4, NONE);
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JR2_P(53, SFP5, NONE);
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JR2_P(54, SFP6, NONE);
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JR2_P(55, SFP7, NONE);
|
||||
JR2_P(56, MIIM1, SFP12);
|
||||
JR2_P(57, MIIM1, SFP13);
|
||||
JR2_P(58, MIIM2, SFP14);
|
||||
JR2_P(59, MIIM2, SFP15);
|
||||
JR2_P(60, NONE, NONE);
|
||||
JR2_P(61, NONE, NONE);
|
||||
JR2_P(62, NONE, NONE);
|
||||
JR2_P(63, NONE, NONE);
|
||||
|
||||
#define JR2_PIN(n) { \
|
||||
.name = "GPIO_"#n, \
|
||||
.drv_data = &jr2_pin_##n \
|
||||
}
|
||||
|
||||
static const struct mscc_pin_data jr2_pins[] = {
|
||||
JR2_PIN(0),
|
||||
JR2_PIN(1),
|
||||
JR2_PIN(2),
|
||||
JR2_PIN(3),
|
||||
JR2_PIN(4),
|
||||
JR2_PIN(5),
|
||||
JR2_PIN(6),
|
||||
JR2_PIN(7),
|
||||
JR2_PIN(8),
|
||||
JR2_PIN(9),
|
||||
JR2_PIN(10),
|
||||
JR2_PIN(11),
|
||||
JR2_PIN(12),
|
||||
JR2_PIN(13),
|
||||
JR2_PIN(14),
|
||||
JR2_PIN(15),
|
||||
JR2_PIN(16),
|
||||
JR2_PIN(17),
|
||||
JR2_PIN(18),
|
||||
JR2_PIN(19),
|
||||
JR2_PIN(20),
|
||||
JR2_PIN(21),
|
||||
JR2_PIN(22),
|
||||
JR2_PIN(23),
|
||||
JR2_PIN(24),
|
||||
JR2_PIN(25),
|
||||
JR2_PIN(26),
|
||||
JR2_PIN(27),
|
||||
JR2_PIN(28),
|
||||
JR2_PIN(29),
|
||||
JR2_PIN(30),
|
||||
JR2_PIN(31),
|
||||
JR2_PIN(32),
|
||||
JR2_PIN(33),
|
||||
JR2_PIN(34),
|
||||
JR2_PIN(35),
|
||||
JR2_PIN(36),
|
||||
JR2_PIN(37),
|
||||
JR2_PIN(38),
|
||||
JR2_PIN(39),
|
||||
JR2_PIN(40),
|
||||
JR2_PIN(41),
|
||||
JR2_PIN(42),
|
||||
JR2_PIN(43),
|
||||
JR2_PIN(44),
|
||||
JR2_PIN(45),
|
||||
JR2_PIN(46),
|
||||
JR2_PIN(47),
|
||||
JR2_PIN(48),
|
||||
JR2_PIN(49),
|
||||
JR2_PIN(50),
|
||||
JR2_PIN(51),
|
||||
JR2_PIN(52),
|
||||
JR2_PIN(53),
|
||||
JR2_PIN(54),
|
||||
JR2_PIN(55),
|
||||
JR2_PIN(56),
|
||||
JR2_PIN(57),
|
||||
JR2_PIN(58),
|
||||
JR2_PIN(59),
|
||||
JR2_PIN(60),
|
||||
JR2_PIN(61),
|
||||
JR2_PIN(62),
|
||||
JR2_PIN(63),
|
||||
};
|
||||
|
||||
static const unsigned long jr2_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x08,
|
||||
[MSCC_GPIO_OUT] = 0x10,
|
||||
[MSCC_GPIO_IN] = 0x18,
|
||||
[MSCC_GPIO_OE] = 0x20,
|
||||
[MSCC_GPIO_INTR] = 0x28,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x30,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x38,
|
||||
[MSCC_GPIO_ALT0] = 0x40,
|
||||
[MSCC_GPIO_ALT1] = 0x48,
|
||||
};
|
||||
|
||||
static int jr2_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
|
||||
uc_priv = dev_get_uclass_priv(dev);
|
||||
uc_priv->bank_name = "jr2-gpio";
|
||||
uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct driver jr2_gpio_driver = {
|
||||
.name = "jr2-gpio",
|
||||
.id = UCLASS_GPIO,
|
||||
.probe = jr2_gpio_probe,
|
||||
.ops = &mscc_gpio_ops,
|
||||
};
|
||||
|
||||
static int jr2_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
|
||||
ARRAY_SIZE(jr2_pins),
|
||||
jr2_function_names,
|
||||
jr2_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
|
||||
dev_of_offset(dev), NULL);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id jr2_pinctrl_of_match[] = {
|
||||
{ .compatible = "mscc,jaguar2-pinctrl" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(jr2_pinctrl) = {
|
||||
.name = "jr2-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(jr2_pinctrl_of_match),
|
||||
.probe = jr2_pinctrl_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
|
||||
.ops = &mscc_pinctrl_ops,
|
||||
};
|
||||
@ -123,6 +123,19 @@ static const struct mscc_pin_data luton_pins[] = {
|
||||
LUTON_PIN(31),
|
||||
};
|
||||
|
||||
static const unsigned long luton_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x04,
|
||||
[MSCC_GPIO_OUT] = 0x08,
|
||||
[MSCC_GPIO_IN] = 0x0c,
|
||||
[MSCC_GPIO_OE] = 0x10,
|
||||
[MSCC_GPIO_INTR] = 0x14,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x18,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x1c,
|
||||
[MSCC_GPIO_ALT0] = 0x20,
|
||||
[MSCC_GPIO_ALT1] = 0x24,
|
||||
};
|
||||
|
||||
static int luton_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
@ -146,7 +159,8 @@ int luton_pinctrl_probe(struct udevice *dev)
|
||||
int ret;
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
|
||||
ARRAY_SIZE(luton_pins), luton_function_names);
|
||||
ARRAY_SIZE(luton_pins), luton_function_names,
|
||||
luton_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -138,6 +138,19 @@ static const struct mscc_pin_data ocelot_pins[] = {
|
||||
OCELOT_PIN(21),
|
||||
};
|
||||
|
||||
static const unsigned long ocelot_gpios[] = {
|
||||
[MSCC_GPIO_OUT_SET] = 0x00,
|
||||
[MSCC_GPIO_OUT_CLR] = 0x04,
|
||||
[MSCC_GPIO_OUT] = 0x08,
|
||||
[MSCC_GPIO_IN] = 0x0c,
|
||||
[MSCC_GPIO_OE] = 0x10,
|
||||
[MSCC_GPIO_INTR] = 0x14,
|
||||
[MSCC_GPIO_INTR_ENA] = 0x18,
|
||||
[MSCC_GPIO_INTR_IDENT] = 0x1c,
|
||||
[MSCC_GPIO_ALT0] = 0x20,
|
||||
[MSCC_GPIO_ALT1] = 0x24,
|
||||
};
|
||||
|
||||
static int ocelot_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv;
|
||||
@ -162,7 +175,8 @@ int ocelot_pinctrl_probe(struct udevice *dev)
|
||||
|
||||
ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
|
||||
ARRAY_SIZE(ocelot_pins),
|
||||
ocelot_function_names);
|
||||
ocelot_function_names,
|
||||
ocelot_gpios);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user