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* Patches by Pantelis Antoniou, 30 Mar 2004:

Browse Source 
- add auto-complete support to the U-Boot CLI
  - add support for NETTA and NETPHONE boards; fix NETVIA board

* Patch by Yuli Barcohen, 28 Mar 2004:
  - Add support for MPC8272 family including MPC8247/8248/8271/8272
  - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
  - Change configuration method for MPC8260ADS family
This commit is contained in:
wdenk
2004-04-15 18:22:41 +00:00
parent d716b12671
commit 04a85b3b36
40 changed files with 7559 additions and 221 deletions
Download Patch File Download Diff File Expand all files Collapse all files

253
board/mpc8260ads/mpc8260ads.c
View File

@@ -9,7 +9,7 @@
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Added support for the 16M dram simm on the 8260ads boards
*
* (C) Copyright 2003 Arabella Software Ltd.
* (C) Copyright 2003-2004 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
*
@@ -47,121 +47,137 @@
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
/* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
/* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
/* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
/* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
/* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
/* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
#if CONFIG_ADSTYPE == CFG_8272ADS
/* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
/* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
#else
/* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
#if CONFIG_ADSTYPE == CFG_8272ADS
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
#else
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
@@ -198,19 +214,25 @@ void reset_phy (void)
{
vu_long *bcsr = (vu_long *)CFG_BCSR;
/* reset the FEC port */
bcsr[1] &= ~FETH1_RST;
/* Reset the PHY */
#if CFG_PHY_ADDR == 0
bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
udelay(2);
bcsr[1] |= FETH1_RST;
#else
bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
udelay(2);
bcsr[3] |= FETH2_RST;
#endif /* CFG_PHY_ADDR == 0 */
udelay(1000);
#ifdef CONFIG_MII
#if CONFIG_ADSTYPE == CFG_PQ2FADS
#if CONFIG_ADSTYPE >= CFG_PQ2FADS
/*
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
miiphy_write(0, 16, 0x610);
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
miiphy_write(CFG_PHY_ADDR, 16, 0x610);
miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
* Ethernet PHY is configured (by means of configuration pins)
@@ -218,9 +240,9 @@ void reset_phy (void)
* to advertise all capabilities, including 100Mb/s, and
* restart autonegotiation.
*/
miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}
@@ -229,7 +251,12 @@ int board_early_init_f (void)
{
vu_long *bcsr = (vu_long *)CFG_BCSR;
bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
bcsr[1] &= ~RS232EN_1;
#endif
#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
bcsr[1] &= ~RS232EN_2;
#endif
#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
#if CONFIG_ADSTYPE == CFG_PQ2FADS
@@ -252,8 +279,10 @@ int board_early_init_f (void)
long int initdram (int board_type)
{
#if CONFIG_ADSTYPE == CFG_PQ2FADS
#if CONFIG_ADSTYPE == CFG_PQ2FADS
long int msize = 32;
#elif CONFIG_ADSTYPE == CFG_8272ADS
long int msize = 64;
#else
long int msize = 16;
#endif
@@ -470,6 +499,8 @@ int checkboard (void)
puts ("Board: Motorola MPC8266ADS\n");
#elif CONFIG_ADSTYPE == CFG_PQ2FADS
puts ("Board: Motorola PQ2FADS-ZU\n");
#elif CONFIG_ADSTYPE == CFG_8272ADS
puts ("Board: Motorola MPC8272ADS\n");
#else
puts ("Board: unknown\n");
#endif

40
board/netphone/Makefile Normal file
View File

@@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o phone_console.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

28
board/netphone/config.mk Normal file
View File

@@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# netVia Boards
#
TEXT_BASE = 0x40000000

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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_byte(flash_info_t * info, ulong dest, uchar data);
static void flash_get_offsets(ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size << 20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#ifdef CFG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
flash_info[0].size = size;
return (size);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_MX:
printf("MXIC ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
uchar mid;
uchar pid;
vu_char *caddr = (vu_char *) addr;
ulong base = (ulong) addr;
/* Write auto select command: read Manufacturer ID */
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
mid = caddr[0];
switch (mid) {
case (AMD_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_FUJ;
break;
case (MX_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_MX;
break;
case (STM_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
pid = caddr[1]; /* device ID */
switch (pid) {
case (AMD_ID_LV400T & 0xFF):
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV400B & 0xFF):
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV800T & 0xFF):
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV800B & 0xFF):
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV160T & 0xFF):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV160B & 0xFF):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
case (STM_ID_M29W040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
#if 0 /* enable when device IDs are available */
case (AMD_ID_LV320T & 0xFF):
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV320B & 0xFF):
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
printf(" ");
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection: D0 = 1 if protected */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
caddr = (vu_char *) info->start[0];
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0xF0;
udelay(20000);
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
vu_char *addr = (vu_char *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_char *) (info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_char *) info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
while (cnt > 0) {
if ((rc = write_byte(info, addr++, *src++)) != 0) {
return (rc);
}
--cnt;
}
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_byte(flash_info_t * info, ulong dest, uchar data)
{
vu_char *addr = (vu_char *) (info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_char *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*((vu_char *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetTA4 board
*/
#include <common.h>
#include <miiphy.h>
#include <sed156x.h>
#include "mpc8xx.h"
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif
/****************************************************************/
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
/****************************************************************/
/*
* Check Board Identity:
*
* Return 1 always.
*/
int checkboard(void)
{
printf ("Intracom NetPhone\n");
return (0);
}
/****************************************************************/
#define _NOT_USED_ 0xFFFFFFFF
/****************************************************************/
#define CS_0000 0x00000000
#define CS_0001 0x10000000
#define CS_0010 0x20000000
#define CS_0011 0x30000000
#define CS_0100 0x40000000
#define CS_0101 0x50000000
#define CS_0110 0x60000000
#define CS_0111 0x70000000
#define CS_1000 0x80000000
#define CS_1001 0x90000000
#define CS_1010 0xA0000000
#define CS_1011 0xB0000000
#define CS_1100 0xC0000000
#define CS_1101 0xD0000000
#define CS_1110 0xE0000000
#define CS_1111 0xF0000000
#define BS_0000 0x00000000
#define BS_0001 0x01000000
#define BS_0010 0x02000000
#define BS_0011 0x03000000
#define BS_0100 0x04000000
#define BS_0101 0x05000000
#define BS_0110 0x06000000
#define BS_0111 0x07000000
#define BS_1000 0x08000000
#define BS_1001 0x09000000
#define BS_1010 0x0A000000
#define BS_1011 0x0B000000
#define BS_1100 0x0C000000
#define BS_1101 0x0D000000
#define BS_1110 0x0E000000
#define BS_1111 0x0F000000
#define A10_AAAA 0x00000000
#define A10_AAA0 0x00200000
#define A10_AAA1 0x00300000
#define A10_000A 0x00800000
#define A10_0000 0x00A00000
#define A10_0001 0x00B00000
#define A10_111A 0x00C00000
#define A10_1110 0x00E00000
#define A10_1111 0x00F00000
#define RAS_0000 0x00000000
#define RAS_0001 0x00040000
#define RAS_1110 0x00080000
#define RAS_1111 0x000C0000
#define CAS_0000 0x00000000
#define CAS_0001 0x00010000
#define CAS_1110 0x00020000
#define CAS_1111 0x00030000
#define WE_0000 0x00000000
#define WE_0001 0x00004000
#define WE_1110 0x00008000
#define WE_1111 0x0000C000
#define GPL4_0000 0x00000000
#define GPL4_0001 0x00001000
#define GPL4_1110 0x00002000
#define GPL4_1111 0x00003000
#define GPL5_0000 0x00000000
#define GPL5_0001 0x00000400
#define GPL5_1110 0x00000800
#define GPL5_1111 0x00000C00
#define LOOP 0x00000080
#define EXEN 0x00000040
#define AMX_COL 0x00000000
#define AMX_ROW 0x00000020
#define AMX_MAR 0x00000030
#define NA 0x00000008
#define UTA 0x00000004
#define TODT 0x00000002
#define LAST 0x00000001
/* #define CAS_LATENCY 3 */
#define CAS_LATENCY 2
const uint sdram_table[0x40] = {
#if CAS_LATENCY == 3
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
#endif
#if CAS_LATENCY == 2
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
_NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
#endif
/* UPT */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* EXC */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
_NOT_USED_,
/* REG */
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
};
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
/* 8 */
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
void check_ram(unsigned int addr, unsigned int size)
{
unsigned int i, j, v, vv;
volatile unsigned int *p;
unsigned int pv;
p = (unsigned int *)addr;
pv = (unsigned int)p;
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
*p++ = pv;
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
v = (unsigned int)p;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
p++;
}
for (j = 0; j < 5; j++) {
switch (j) {
case 0: v = 0x00000000; break;
case 1: v = 0xffffffff; break;
case 2: v = 0x55555555; break;
case 3: v = 0xaaaaaaaa; break;
default:v = 0xdeadbeef; break;
}
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
*p = v;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
*p = ~v;
p++;
}
}
}
long int initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
/*
* Preliminary prescaler for refresh
*/
memctl->memc_mptpr = MPTPR_PTP_DIV8;
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
/* perform SDRAM initialisation sequence */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
udelay(1);
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
udelay(10000);
{
u32 d1, d2;
d1 = 0xAA55AA55;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
d1 = 0x55AA55AA;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
}
size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
#if 0
printf("check 0\n");
check_ram(( 0 << 20), (2 << 20));
printf("check 16\n");
check_ram((16 << 20), (2 << 20));
printf("check 32\n");
check_ram((32 << 20), (2 << 20));
printf("check 48\n");
check_ram((48 << 20), (2 << 20));
#endif
if (size == 0) {
printf("SIZE is zero: LOOP on 0\n");
for (;;) {
*(volatile u32 *)0 = 0;
(void)*(volatile u32 *)0;
}
}
return size;
}
/* ------------------------------------------------------------------------- */
void reset_phys(void)
{
int phyno;
unsigned short v;
udelay(10000);
/* reset the damn phys */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
/* ------------------------------------------------------------------------- */
/* GP = general purpose, SP = special purpose (on chip peripheral) */
/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_GP_INMASK 0
#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
#define PA_SP_MASK 0
#define PA_ODR_VAL 0
#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK _B(28)
#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
#define PB_SP_MASK (_BR(22, 25))
#define PB_ODR_VAL 0
#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
#define PB_SP_DIRVAL 0
#define PC_GP_INMASK _BW(12)
#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
#define PC_SP_MASK 0
#define PC_SOVAL 0
#define PC_INTVAL 0
#define PC_GP_OUTVAL (_BW(10) | _BW(11))
#define PC_SP_DIRVAL 0
#define PE_GP_INMASK _B(31)
#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
#define PE_SP_MASK 0
#define PE_ODR_VAL 0
#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
#define PE_SP_DIRVAL 0
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* DSP chip select */
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* External register chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
memctl->memc_br5 &= ~BR_V;
memctl->memc_br6 &= ~BR_V;
memctl->memc_br7 &= ~BR_V;
ioport->iop_padat = PA_GP_OUTVAL;
ioport->iop_paodr = PA_ODR_VAL;
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
ioport->iop_papar = PA_SP_MASK;
cpm->cp_pbdat = PB_GP_OUTVAL;
cpm->cp_pbodr = PB_ODR_VAL;
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
cpm->cp_pbpar = PB_SP_MASK;
ioport->iop_pcdat = PC_GP_OUTVAL;
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
ioport->iop_pcso = PC_SOVAL;
ioport->iop_pcint = PC_INTVAL;
ioport->iop_pcpar = PC_SP_MASK;
cpm->cp_pedat = PE_GP_OUTVAL;
cpm->cp_peodr = PE_ODR_VAL;
cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
cpm->cp_pepar = PE_SP_MASK;
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen;
totlen = nand_probe(CFG_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
/* XXX add here the really funky stuff */
}
#endif
#ifdef CONFIG_SHOW_ACTIVITY
static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
/* called from timer interrupt every 1/CFG_HZ sec */
void board_show_activity(ulong timestamp)
{
if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
--left_to_poll;
}
extern void phone_console_do_poll(void);
static void do_poll(void)
{
unsigned int base;
while (left_to_poll <= 0) {
phone_console_do_poll();
base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
do {
left_to_poll = base;
} while (base != left_to_poll);
}
}
/* called when looping */
void show_activity(int arg)
{
do_poll();
}
#endif
#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
int overwrite_console(void)
{
/* printf("overwrite_console called\n"); */
return 0;
}
#endif
extern int drv_phone_init(void);
extern int drv_phone_use_me(void);
int misc_init_r(void)
{
return drv_phone_init();
}
int last_stage_init(void)
{
int i;
reset_phys();
/* check in order to enable the local console */
left_to_poll = PHONE_CONSOLE_POLL_HZ;
i = CFG_HZ * 2;
while (i > 0) {
if (tstc()) {
getc();
break;
}
do_poll();
if (drv_phone_use_me()) {
console_assign(stdin, "phone");
console_assign(stdout, "phone");
console_assign(stderr, "phone");
setenv("bootdelay", "-1");
break;
}
udelay(1000000 / CFG_HZ);
i--;
left_to_poll--;
}
left_to_poll = PHONE_CONSOLE_POLL_HZ;
return 0;
}

1122
board/netphone/phone_console.c Normal file
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File diff suppressed because it is too large Load Diff

138
board/netphone/u-boot.lds Normal file
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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

135
board/netphone/u-boot.lds.debug Normal file
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@@ -0,0 +1,135 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

40
board/netta/Makefile Normal file
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@@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o dsp.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

28
board/netta/config.mk Normal file
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@@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# netVia Boards
#
TEXT_BASE = 0x40000000

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board/netta/dsp.c Normal file
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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_byte(flash_info_t * info, ulong dest, uchar data);
static void flash_get_offsets(ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#ifdef CFG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
flash_info[0].size = size;
return (size);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_MX:
printf("MXIC ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
uchar mid;
uchar pid;
vu_char *caddr = (vu_char *) addr;
ulong base = (ulong) addr;
/* Write auto select command: read Manufacturer ID */
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
mid = caddr[0];
switch (mid) {
case (AMD_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_FUJ;
break;
case (MX_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_MX;
break;
case (STM_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
pid = caddr[1]; /* device ID */
switch (pid) {
case (AMD_ID_LV400T & 0xFF):
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV400B & 0xFF):
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV800T & 0xFF):
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV800B & 0xFF):
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV160T & 0xFF):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV160B & 0xFF):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
case (STM_ID_M29W040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
#if 0 /* enable when device IDs are available */
case (AMD_ID_LV320T & 0xFF):
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV320B & 0xFF):
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
printf(" ");
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection: D0 = 1 if protected */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
caddr = (vu_char *) info->start[0];
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0xF0;
udelay(20000);
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
vu_char *addr = (vu_char *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_char *) (info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_char *) info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
while (cnt > 0) {
if ((rc = write_byte(info, addr++, *src++)) != 0) {
return (rc);
}
--cnt;
}
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_byte(flash_info_t * info, ulong dest, uchar data)
{
vu_char *addr = (vu_char *) (info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_char *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*((vu_char *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

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board/netta/netta.c Normal file
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/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetTA4 board
*/
#include <common.h>
#include <miiphy.h>
#include "mpc8xx.h"
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif
/****************************************************************/
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
/****************************************************************/
/*
* Check Board Identity:
*
* Return 1 always.
*/
int checkboard(void)
{
printf ("Intracom NETTA"
#if defined(CONFIG_NETTA_ISDN)
" with ISDN support"
#endif
"\n"
);
return (0);
}
/****************************************************************/
#define _NOT_USED_ 0xFFFFFFFF
/****************************************************************/
#define CS_0000 0x00000000
#define CS_0001 0x10000000
#define CS_0010 0x20000000
#define CS_0011 0x30000000
#define CS_0100 0x40000000
#define CS_0101 0x50000000
#define CS_0110 0x60000000
#define CS_0111 0x70000000
#define CS_1000 0x80000000
#define CS_1001 0x90000000
#define CS_1010 0xA0000000
#define CS_1011 0xB0000000
#define CS_1100 0xC0000000
#define CS_1101 0xD0000000
#define CS_1110 0xE0000000
#define CS_1111 0xF0000000
#define BS_0000 0x00000000
#define BS_0001 0x01000000
#define BS_0010 0x02000000
#define BS_0011 0x03000000
#define BS_0100 0x04000000
#define BS_0101 0x05000000
#define BS_0110 0x06000000
#define BS_0111 0x07000000
#define BS_1000 0x08000000
#define BS_1001 0x09000000
#define BS_1010 0x0A000000
#define BS_1011 0x0B000000
#define BS_1100 0x0C000000
#define BS_1101 0x0D000000
#define BS_1110 0x0E000000
#define BS_1111 0x0F000000
#define A10_AAAA 0x00000000
#define A10_AAA0 0x00200000
#define A10_AAA1 0x00300000
#define A10_000A 0x00800000
#define A10_0000 0x00A00000
#define A10_0001 0x00B00000
#define A10_111A 0x00C00000
#define A10_1110 0x00E00000
#define A10_1111 0x00F00000
#define RAS_0000 0x00000000
#define RAS_0001 0x00040000
#define RAS_1110 0x00080000
#define RAS_1111 0x000C0000
#define CAS_0000 0x00000000
#define CAS_0001 0x00010000
#define CAS_1110 0x00020000
#define CAS_1111 0x00030000
#define WE_0000 0x00000000
#define WE_0001 0x00004000
#define WE_1110 0x00008000
#define WE_1111 0x0000C000
#define GPL4_0000 0x00000000
#define GPL4_0001 0x00001000
#define GPL4_1110 0x00002000
#define GPL4_1111 0x00003000
#define GPL5_0000 0x00000000
#define GPL5_0001 0x00000400
#define GPL5_1110 0x00000800
#define GPL5_1111 0x00000C00
#define LOOP 0x00000080
#define EXEN 0x00000040
#define AMX_COL 0x00000000
#define AMX_ROW 0x00000020
#define AMX_MAR 0x00000030
#define NA 0x00000008
#define UTA 0x00000004
#define TODT 0x00000002
#define LAST 0x00000001
/* #define CAS_LATENCY 3 */
#define CAS_LATENCY 2
const uint sdram_table[0x40] = {
#if CAS_LATENCY == 3
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
#endif
#if CAS_LATENCY == 2
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_,
_NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
#endif
/* UPT */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* EXC */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
_NOT_USED_,
/* REG */
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
};
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
/* 8 */
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
void check_ram(unsigned int addr, unsigned int size)
{
unsigned int i, j, v, vv;
volatile unsigned int *p;
unsigned int pv;
p = (unsigned int *)addr;
pv = (unsigned int)p;
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
*p++ = pv;
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
v = (unsigned int)p;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
p++;
}
for (j = 0; j < 5; j++) {
switch (j) {
case 0: v = 0x00000000; break;
case 1: v = 0xffffffff; break;
case 2: v = 0x55555555; break;
case 3: v = 0xaaaaaaaa; break;
default:v = 0xdeadbeef; break;
}
p = (unsigned int *)addr;
for (i = 0; i < size / sizeof(unsigned int); i++) {
*p = v;
vv = *p;
if (vv != v) {
printf("%p: read %08x instead of %08x\n", p, vv, v);
hang();
}
*p = ~v;
p++;
}
}
}
long int initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
/*
* Preliminary prescaler for refresh
*/
memctl->memc_mptpr = MPTPR_PTP_DIV8;
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
/* perform SDRAM initialisation sequence */
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
udelay(1);
memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
udelay(10000);
{
u32 d1, d2;
d1 = 0xAA55AA55;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
d1 = 0x55AA55AA;
*(volatile u32 *)0 = d1;
d2 = *(volatile u32 *)0;
if (d1 != d2) {
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
hang();
}
}
size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
#if 0
printf("check 0\n");
check_ram(( 0 << 20), (2 << 20));
printf("check 16\n");
check_ram((16 << 20), (2 << 20));
printf("check 32\n");
check_ram((32 << 20), (2 << 20));
printf("check 48\n");
check_ram((48 << 20), (2 << 20));
#endif
if (size == 0) {
printf("SIZE is zero: LOOP on 0\n");
for (;;) {
*(volatile u32 *)0 = 0;
(void)*(volatile u32 *)0;
}
}
return size;
}
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
{
return(0);
}
void reset_phys(void)
{
int phyno;
unsigned short v;
/* reset the damn phys */
mii_init();
for (phyno = 0; phyno < 32; ++phyno) {
miiphy_read(phyno, PHY_PHYIDR1, &v);
if (v == 0xFFFF)
continue;
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
udelay(10000);
miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
udelay(10000);
}
}
extern int board_dsp_reset(void);
int last_stage_init(void)
{
int r;
reset_phys();
r = board_dsp_reset();
if (r < 0)
printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
return 0;
}
/* ------------------------------------------------------------------------- */
/* GP = general purpose, SP = special purpose (on chip peripheral) */
/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11))
#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15))
#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5))
#define PA_ODR_VAL 0
#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15))
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK (_B(28) | _B(31))
#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 30))
#define PB_SP_MASK (_BR(22, 25))
#define PB_ODR_VAL 0
#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_DIRVAL 0
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
#define PC_GP_OUTMASK (_BW(6) | _BW(12))
#define PC_SP_MASK (_BW(4) | _BW(8))
#define PC_SOVAL 0
#define PC_INTVAL _BW(7)
#define PC_GP_OUTVAL (_BW(6) | _BW(12))
#define PC_SP_DIRVAL 0
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
#define PD_SP_DIRVAL 0
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* CS1: NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* CS2: DSP */
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* CS4: External register chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
/* CS5: dummy for accurate delay */
memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
ioport->iop_padat = PA_GP_OUTVAL;
ioport->iop_paodr = PA_ODR_VAL;
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
ioport->iop_papar = PA_SP_MASK;
cpm->cp_pbdat = PB_GP_OUTVAL;
cpm->cp_pbodr = PB_ODR_VAL;
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
cpm->cp_pbpar = PB_SP_MASK;
ioport->iop_pcdat = PC_GP_OUTVAL;
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
ioport->iop_pcso = PC_SOVAL;
ioport->iop_pcint = PC_INTVAL;
ioport->iop_pcpar = PC_SP_MASK;
ioport->iop_pddat = PD_GP_OUTVAL;
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
ioport->iop_pdpar = PD_SP_MASK;
ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7));
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern ulong nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
unsigned long totlen = nand_probe(CFG_NAND_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
int pcmcia_init(void)
{
return 0;
}
#endif
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif
#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
/* XXX add here the really funky stuff */
}
#endif

138
board/netta/u-boot.lds Normal file
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@@ -0,0 +1,138 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

135
board/netta/u-boot.lds.debug Normal file
View File

@@ -0,0 +1,135 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}