mpc8xx: remove fads board support
These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
committed by
Tom Rini
Tom Rini
parent
c51c1c9af9
commit
03f9d7d174
@@ -56,9 +56,6 @@
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GOT_ENTRY(__init_end)
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GOT_ENTRY(__bss_end)
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GOT_ENTRY(__bss_start)
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#if defined(CONFIG_FADS)
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GOT_ENTRY(environment)
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#endif
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END_GOT
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/*
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@@ -97,14 +97,8 @@ static int check_CPU (long clock, uint pvr, uint immr)
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pre = 'M'; m = 1;
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if (id_str == NULL)
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id_str =
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# if defined(CONFIG_MPC852T)
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"PC852T";
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# elif defined(CONFIG_MPC859T)
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# if defined(CONFIG_MPC859T)
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"PC859T";
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# elif defined(CONFIG_MPC859DSL)
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"PC859DSL";
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# elif defined(CONFIG_MPC866T)
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"PC866T";
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# else
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"PC866x"; /* Unknown chip from MPC866 family */
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# endif
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@@ -542,32 +542,6 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
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int i;
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if (efis->ether_index == 0) {
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#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
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#if defined(CONFIG_MPC885ADS)
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*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
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#else
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/* configure FADS for fast (FEC) ethernet, half-duplex */
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/* The LXT970 needs about 50ms to recover from reset, so
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* wait for it by discovering the PHY before leaving eth_init().
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*/
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{
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volatile uint *bcsr4 = (volatile uint *) BCSR4;
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*bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
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| (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
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BCSR4_FETHRST);
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/* reset the LXT970 PHY */
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*bcsr4 &= ~BCSR4_FETHRST;
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udelay (10);
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*bcsr4 |= BCSR4_FETHRST;
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udelay (10);
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}
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#endif /* CONFIG_MPC885ADS */
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#endif /* CONFIG_FADS */
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* the MII interface is connected to FEC1
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* so for the miiphy_xxx function to work we must
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@@ -197,19 +197,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
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reset_phy();
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#endif
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#ifdef CONFIG_FADS
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
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/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
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*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
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*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
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*((uint *) BCSR1) &= ~BCSR1_ETHEN;
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#else
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*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
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*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
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*((uint *) BCSR1) &= ~BCSR1_ETHEN;
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#endif
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#endif
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pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
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rxIdx = 0;
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@@ -488,13 +475,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
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immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
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(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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/*
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* Work around transmit problem with first eth packet
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*/
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#if defined (CONFIG_FADS)
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udelay (10000); /* wait 10 ms */
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#endif
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return 1;
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}
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@@ -173,15 +173,6 @@ static int smc_init (void)
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# endif
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#endif
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#if defined(CONFIG_FADS)
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/* Enable RS232 */
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#if defined(CONFIG_8xx_CONS_SMC1)
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*((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
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#else
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*((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
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#endif
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#endif /* CONFIG_FADS */
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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@@ -798,22 +798,6 @@ static void video_encoder_init (void)
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i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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#ifdef CONFIG_FADS
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/* Reset ADV7176 chip */
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debug ("[VIDEO ENCODER] Resetting encoder...\n");
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(*(int *) BCSR4) &= ~(1 << 21);
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/* Wait for 5 ms inside the reset */
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debug ("[VIDEO ENCODER] Waiting for encoder reset...\n");
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udelay (5000);
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/* Take ADV7176 out of reset */
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(*(int *) BCSR4) |= 1 << 21;
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/* Wait for 5 ms after the reset */
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udelay (5000);
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#endif /* CONFIG_FADS */
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/* Send configuration */
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#ifdef DEBUG
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{
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@@ -860,16 +844,6 @@ static void video_ctrl_init (void *memptr)
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debug ("[VIDEO CTRL] Turning off video controller...\n");
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SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0);
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#ifdef CONFIG_FADS
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/* Turn on Video Port LED */
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debug ("[VIDEO CTRL] Turning off video port led...\n");
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SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1);
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/* Disable internal clock */
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debug ("[VIDEO CTRL] Disabling internal clock...\n");
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SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0);
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#endif
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/* Generate and make active a new video mode */
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debug ("[VIDEO CTRL] Generating video mode...\n");
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video_mode_generate ();
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@@ -892,15 +866,6 @@ static void video_ctrl_init (void *memptr)
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immap->im_ioport.iop_pdpar = 0x1fff;
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immap->im_ioport.iop_pddir = 0x0000;
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#ifdef CONFIG_FADS
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/* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */
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debug ("[VIDEO CTRL] Turning on video clock...\n");
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SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1);
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/* Turn on Video Port LED */
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debug ("[VIDEO CTRL] Turning on video port led...\n");
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SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
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#endif
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#ifdef CONFIG_RRVISION
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debug ("PC5->Output(1): enable PAL clock");
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immap->im_ioport.iop_pcpar &= ~(0x0400);
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@@ -1153,9 +1118,7 @@ static void *video_logo (void)
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{
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u16 *screen = video_fb_address, width = VIDEO_COLS;
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#ifdef VIDEO_INFO
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# ifndef CONFIG_FADS
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char temp[32];
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# endif
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char info[80];
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#endif /* VIDEO_INFO */
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@@ -1173,7 +1136,7 @@ static void *video_logo (void)
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sprintf (info, " Wolfgang DENK, wd@denx.de");
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video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
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info);
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#ifndef CONFIG_FADS /* all normal boards */
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/* leave one blank line */
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sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash",
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@@ -1182,15 +1145,6 @@ static void *video_logo (void)
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gd->bd->bi_flashsize >> 20 );
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video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4,
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info);
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#else /* FADS :-( */
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sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board");
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video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
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info);
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sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM");
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video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
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info);
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#endif
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#endif
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return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN;
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