board: gateworks: imx8mm: Add Gateworks Venice board support

Add initial support for Gateworks Venice product family based on the
i.MX 8M Mini SoC

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

board/gateworks/venice/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_VENICE
+
+config SYS_BOARD
+	default "venice"
+
+config SYS_VENDOR
+	default "gateworks"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_venice"
+
+endif

board/gateworks/venice/MAINTAINERS

@@ -0,0 +1,7 @@
+i.MX8MM Venice
+M:	Tim Harvey <tharvey@gateworks.com>
+S:	Maintained
+F:	arch/arm/dts/imx8mm-venice*
+F:	board/gateworks/venice/
+F:	include/configs/venice.h
+F:	configs/imx8mm_venice_defconfig

board/gateworks/venice/Makefile

@@ -0,0 +1,12 @@
+#
+# Copyright 2021 Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_venice.o gsc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif

board/gateworks/venice/README

@@ -0,0 +1,34 @@
+U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
+$ cp build/imx8mm/release/bl31.bin .
+
+Get the DDR Firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ make imx8mm_venice_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Update eMMC
+===========
+=> tftpboot $loadaddr flash.bin
+=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
+=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt

board/gateworks/venice/gsc.c

@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hang.h>
+#include <hexdump.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct venice_board_info som_info;
+struct venice_board_info base_info;
+char venice_model[32];
+
+/* return a mac address from EEPROM info */
+int gsc_getmac(int index, uint8_t *address)
+{
+	int i, j;
+	u32 maclow, machigh;
+	u64 mac;
+
+	j = 0;
+	if (som_info.macno) {
+		maclow = som_info.mac[5];
+		maclow |= som_info.mac[4] << 8;
+		maclow |= som_info.mac[3] << 16;
+		maclow |= som_info.mac[2] << 24;
+		machigh = som_info.mac[1];
+		machigh |= som_info.mac[0] << 8;
+		mac = machigh;
+		mac <<= 32;
+		mac |= maclow;
+		for (i = 0; i < som_info.macno; i++, j++) {
+			if (index == j)
+				goto out;
+		}
+	}
+
+	maclow = base_info.mac[5];
+	maclow |= base_info.mac[4] << 8;
+	maclow |= base_info.mac[3] << 16;
+	maclow |= base_info.mac[2] << 24;
+	machigh = base_info.mac[1];
+	machigh |= base_info.mac[0] << 8;
+	mac = machigh;
+	mac <<= 32;
+	mac |= maclow;
+	for (i = 0; i < base_info.macno; i++, j++) {
+		if (index == j)
+			goto out;
+	}
+
+	return -EINVAL;
+
+out:
+	mac += i;
+	address[0] = (mac >> 40) & 0xff;
+	address[1] = (mac >> 32) & 0xff;
+	address[2] = (mac >> 24) & 0xff;
+	address[3] = (mac >> 16) & 0xff;
+	address[4] = (mac >> 8) & 0xff;
+	address[5] = (mac >> 0) & 0xff;
+
+	return 0;
+}
+
+/* System Controller registers */
+enum {
+	GSC_SC_CTRL0		= 0,
+	GSC_SC_CTRL1		= 1,
+	GSC_SC_STATUS		= 10,
+	GSC_SC_FWCRC		= 12,
+	GSC_SC_FWVER		= 14,
+	GSC_SC_WP		= 15,
+	GSC_SC_RST_CAUSE	= 16,
+	GSC_SC_THERM_PROTECT	= 19,
+};
+
+/* System Controller Control1 bits */
+enum {
+	GSC_SC_CTRL1_WDTIME	= 4, /* 1 = 60s timeout, 0 = 30s timeout */
+	GSC_SC_CTRL1_WDEN	= 5, /* 1 = enable, 0 = disable */
+	GSC_SC_CTRL1_BOOT_CHK   = 6, /* 1 = enable alt boot check */
+	GSC_SC_CTRL1_WDDIS	= 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+	GSC_SC_IRQ_PB		= 0, /* Pushbutton switch */
+	GSC_SC_IRQ_SECURE	= 1, /* Secure Key erase operation complete */
+	GSC_SC_IRQ_EEPROM_WP	= 2, /* EEPROM write violation */
+	GSC_SC_IRQ_GPIO		= 4, /* GPIO change */
+	GSC_SC_IRQ_TAMPER	= 5, /* Tamper detect */
+	GSC_SC_IRQ_WATCHDOG	= 6, /* Watchdog trip */
+	GSC_SC_IRQ_PBLONG	= 7, /* Pushbutton long hold */
+};
+
+/* System Controller WP bits */
+enum {
+	GSC_SC_WP_ALL		= 0, /* Write Protect All EEPROM regions */
+	GSC_SC_WP_BOARDINFO	= 1, /* Write Protect Board Info region */
+};
+
+/* System Controller Reset Cause */
+enum {
+	GSC_SC_RST_CAUSE_VIN		= 0,
+	GSC_SC_RST_CAUSE_PB		= 1,
+	GSC_SC_RST_CAUSE_WDT		= 2,
+	GSC_SC_RST_CAUSE_CPU		= 3,
+	GSC_SC_RST_CAUSE_TEMP_LOCAL	= 4,
+	GSC_SC_RST_CAUSE_TEMP_REMOTE	= 5,
+	GSC_SC_RST_CAUSE_SLEEP		= 6,
+	GSC_SC_RST_CAUSE_BOOT_WDT	= 7,
+	GSC_SC_RST_CAUSE_BOOT_WDT_MAN	= 8,
+	GSC_SC_RST_CAUSE_SOFT_PWR	= 9,
+	GSC_SC_RST_CAUSE_MAX		= 10,
+};
+
+static struct udevice *gsc_get_dev(int busno, int slave)
+{
+	struct udevice *dev;
+	int ret;
+
+#if (IS_ENABLED(CONFIG_SPL_BUILD))
+	ret = i2c_get_chip_for_busnum(busno + 1, slave, 1, &dev);
+	if (ret)
+		return NULL;
+#else
+	struct udevice *bus;
+
+	busno--;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
+	if (ret) {
+		printf("i2c%d: no bus %d\n", busno + 1, ret);
+		return NULL;
+	}
+	ret = i2c_get_chip(bus, slave, 1, &dev);
+	if (ret) {
+		printf("i2c%d@0x%02x: no chip %d\n", busno + 1, slave, ret);
+		return NULL;
+	}
+#endif
+
+	return dev;
+}
+
+static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info)
+{
+	int i;
+	int chksum;
+	unsigned char *buf = (unsigned char *)info;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(bus, slave);
+	if (!dev) {
+		if (slave == GSC_EEPROM_ADDR)
+			puts("ERROR: Failed to probe EEPROM\n");
+		return -ENODEV;
+	}
+
+	/* read eeprom config section */
+	memset(info, 0, sizeof(*info));
+	ret = i2c_set_chip_offset_len(dev, alen);
+	if (ret) {
+		puts("EEPROM: Failed to set alen\n");
+		return ret;
+	}
+	ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info));
+	if (ret) {
+		if (slave == GSC_EEPROM_ADDR)
+			printf("EEPROM: Failed to read EEPROM\n");
+		return ret;
+	}
+
+	/* validate checksum */
+	for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++)
+		chksum += buf[i];
+	if ((info->chksum[0] != chksum >> 8) ||
+	    (info->chksum[1] != (chksum & 0xff))) {
+		printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+		print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+		memset(info, 0, sizeof(*info));
+		return -EINVAL;
+	}
+
+	/* sanity check valid model */
+	if (info->model[0] != 'G' || info->model[1] != 'W') {
+		printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+		print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+		memset(info, 0, sizeof(*info));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const char *gsc_get_rst_cause(struct udevice *dev)
+{
+	static char str[64];
+	static const char * const names[] = {
+		"VIN",
+		"PB",
+		"WDT",
+		"CPU",
+		"TEMP_L",
+		"TEMP_R",
+		"SLEEP",
+		"BOOT_WDT1",
+		"BOOT_WDT2",
+		"SOFT_PWR",
+	};
+	unsigned char reg;
+
+	/* reset cause */
+	str[0] = 0;
+	if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, &reg, 1)) {
+		if (reg < ARRAY_SIZE(names))
+			sprintf(str, "%s", names[reg]);
+		else
+			sprintf(str, "0x%02x", reg);
+	}
+
+	/* thermal protection */
+	if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, &reg, 1)) {
+		reg |= 1;
+		dm_i2c_write(dev, GSC_SC_THERM_PROTECT, &reg, 1);
+		strcat(str, " Thermal Protection Enabled");
+	}
+
+	return str;
+}
+
+/* display hardware monitor ADC channels */
+int gsc_hwmon(void)
+{
+	const void *fdt = gd->fdt_blob;
+	struct udevice *dev;
+	int node, reg, mode, len, val, offset;
+	const char *label;
+	u8 buf[2];
+	int ret;
+
+	node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+	if (node <= 0)
+		return node;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_HWMON_ADDR);
+	if (!dev) {
+		puts("ERROR: Failed to probe GSC HWMON\n");
+		return -ENODEV;
+	}
+
+	/* iterate over hwmon nodes */
+	node = fdt_first_subnode(fdt, node);
+	while (node > 0) {
+		reg = fdtdec_get_int(fdt, node, "reg", -1);
+		mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+		offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
+		label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+		if ((reg == -1) || (mode == -1) || !label)
+			printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+
+		memset(buf, 0, sizeof(buf));
+		ret = dm_i2c_read(dev, reg, buf, sizeof(buf));
+		if (ret) {
+			printf("i2c error: %d\n", ret);
+			continue;
+		}
+		val = buf[0] | buf[1] << 8;
+		if (val >= 0) {
+			const u32 *div;
+			int r[2];
+
+			switch (mode) {
+			case 0: /* temperature (C*10) */
+				if (val > 0x8000)
+					val -= 0xffff;
+				printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+				break;
+			case 1: /* prescaled voltage */
+				if (val != 0xffff)
+					printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+				break;
+			case 2: /* scaled based on ref volt and resolution */
+				val *= 2500;
+				val /= 1 << 12;
+
+				/* apply pre-scaler voltage divider */
+				div  = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
+				if (div && (len == sizeof(uint32_t) * 2)) {
+					r[0] = fdt32_to_cpu(div[0]);
+					r[1] = fdt32_to_cpu(div[1]);
+					if (r[0] && r[1]) {
+						val *= (r[0] + r[1]);
+						val /= r[1];
+					}
+				}
+
+				/* adjust by offset */
+				val += offset;
+
+				printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+				break;
+			}
+		}
+		node = fdt_next_subnode(fdt, node);
+	}
+
+	return 0;
+}
+
+/* determine BOM revision from model */
+int get_bom_rev(const char *str)
+{
+	int  rev_bom = 0;
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= '1' && str[i] <= '9') {
+			rev_bom = str[i] - '0';
+			break;
+		}
+	}
+	return rev_bom;
+}
+
+/* determine PCB revision from model */
+char get_pcb_rev(const char *str)
+{
+	char rev_pcb = 'A';
+	int i;
+
+	for (i = strlen(str) - 1; i > 0; i--) {
+		if (str[i] == '-')
+			break;
+		if (str[i] >= 'A') {
+			rev_pcb = str[i];
+			break;
+		}
+	}
+	return rev_pcb;
+}
+
+/*
+ * get dt name based on model and detail level:
+ *
+ * For boards that are a combination of a SoM plus a Baseboard:
+ *   Venice SoM part numbers are GW70xx where xx is:
+ *    7000-7019: same PCB with som dt of '0x'
+ *    7020-7039: same PCB with som dt of '2x'
+ *    7040-7059: same PCB with som dt of '4x'
+ *    7060-7079: same PCB with som dt of '6x'
+ *    7080-7099: same PCB with som dt of '8x'
+ *   Venice Baseboard part numbers are GW7xxx where xxx is:
+ *    7100-7199: same PCB with base dt of '71xx'
+ *    7200-7299: same PCB with base dt of '72xx'
+ *    7300-7399: same PCB with base dt of '73xx'
+ *    7400-7499: same PCB with base dt of '74xx'
+ *    7500-7599: same PCB with base dt of '75xx'
+ *    7600-7699: same PCB with base dt of '76xx'
+ *    7700-7799: same PCB with base dt of '77xx'
+ *    7800-7899: same PCB with base dt of '78xx'
+ *   DT name is comprised of:
+ *    gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev]
+ *
+ * For board models from 7900-7999 each PCB is unique with its own dt:
+ *   DT name is comprised:
+ *    gw<model>-[pcb-rev][bom-rev]
+ *
+ */
+#define snprintfcat(dest, sz, fmt, ...) \
+	snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
+const char *gsc_get_dtb_name(int level, char *buf, int sz)
+{
+	const char *pre = "imx8mm-venice-gw";
+	int model, rev_pcb, rev_bom;
+
+	model = ((som_info.model[2] - '0') * 1000)
+		+ ((som_info.model[3] - '0') * 100)
+		+ ((som_info.model[4] - '0') * 10)
+		+ (som_info.model[5] - '0');
+	rev_pcb = tolower(get_pcb_rev(som_info.model));
+	rev_bom = get_bom_rev(som_info.model);
+
+	/* som + baseboard*/
+	if (base_info.model[0]) {
+		/* baseboard id: 7100-7199->71; 7200-7299->72; etc */
+		int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0');
+		/* som id: 7000-7019->1; 7020-7039->2; etc */
+		int som = ((model % 100) / 20) * 2;
+		int rev_base_pcb = tolower(get_pcb_rev(base_info.model));
+		int rev_base_bom = get_bom_rev(base_info.model);
+
+		snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
+		switch (level) {
+		case 0: /* full model (ie gw73xx-0x-a1a1) */
+			if (rev_base_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_base_pcb);
+			if (rev_bom)
+				snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "%c", rev_pcb);
+			break;
+		case 1: /* don't care about SoM revision */
+			if (rev_base_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_base_pcb);
+			snprintfcat(buf, sz, "xx");
+			break;
+		case 2: /* don't care about baseboard revision */
+			snprintfcat(buf, sz, "-xx");
+			if (rev_bom)
+				snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "%c", rev_pcb);
+			break;
+		case 3: /* don't care about SoM/baseboard revision */
+			break;
+		default:
+			return NULL;
+		}
+	} else {
+		snprintf(buf, sz, "%s%04d", pre, model);
+		switch (level) {
+		case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */
+			if (rev_bom)
+				snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom);
+			else
+				snprintfcat(buf, sz, "-%c", rev_pcb);
+			break;
+		case 1: /* don't care about BOM revision */
+			snprintfcat(buf, sz, "-%c", rev_pcb);
+			break;
+		case 2: /* don't care about PCB or BOM revision */
+			break;
+		default:
+			return NULL;
+		}
+	}
+
+	return buf;
+}
+
+static int gsc_read(void)
+{
+	int ret;
+
+	ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
+	if (ret) {
+		memset(&som_info, 0, sizeof(som_info));
+		return ret;
+	}
+
+	/* read optional baseboard EEPROM */
+	return gsc_read_eeprom(2, 0x52, 2, &base_info);
+}
+
+static int gsc_info(int verbose)
+{
+	struct udevice *dev;
+	unsigned char buf[16];
+	char rev_pcb;
+	int rev_bom;
+
+	if (!base_info.model[0]) {
+		strcpy(venice_model, som_info.model);
+		printf("Model   : %s\n", som_info.model);
+		printf("Serial  : %d\n", som_info.serial);
+		printf("MFGDate : %02x-%02x-%02x%02x\n",
+		       som_info.mfgdate[0], som_info.mfgdate[1],
+		       som_info.mfgdate[2], som_info.mfgdate[3]);
+	} else {
+		sprintf(venice_model, "GW%c%c%c%c-%c%c-",
+			som_info.model[2], /* family */
+			base_info.model[3], /* baseboard */
+			base_info.model[4], base_info.model[5], /* subload of baseboard */
+			som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
+
+		/* baseboard revision */
+		rev_pcb = get_pcb_rev(base_info.model);
+		rev_bom = get_bom_rev(base_info.model);
+		if (rev_bom)
+			sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+		else
+			sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+		/* som revision */
+		rev_pcb = get_pcb_rev(som_info.model);
+		rev_bom = get_bom_rev(som_info.model);
+		if (rev_bom)
+			sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+		else
+			sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+
+		if (verbose > 1) {
+			printf("SOM     : %s %d %02x-%02x-%02x%02x\n",
+			       som_info.model, som_info.serial,
+			       som_info.mfgdate[0], som_info.mfgdate[1],
+			       som_info.mfgdate[2], som_info.mfgdate[3]);
+			printf("BASE    : %s %d %02x-%02x-%02x%02x\n",
+			       base_info.model, base_info.serial,
+			       base_info.mfgdate[0], base_info.mfgdate[1],
+			       base_info.mfgdate[2], base_info.mfgdate[3]);
+		}
+		printf("Model   : %s\n", venice_model);
+		printf("Serial  : %d\n", som_info.serial);
+		printf("MFGDate : %02x-%02x-%02x%02x\n",
+		       som_info.mfgdate[0], som_info.mfgdate[1],
+		       som_info.mfgdate[2], som_info.mfgdate[3]);
+	}
+
+	/* Display RTC */
+	puts("RTC     : ");
+	dev = gsc_get_dev(1, GSC_RTC_ADDR);
+	if (!dev) {
+		puts("Failed to probe GSC RTC\n");
+	} else {
+		dm_i2c_read(dev, 0, buf, 6);
+		printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
+	}
+
+	return 0;
+}
+
+int gsc_init(int quiet)
+{
+	unsigned char buf[16];
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * On a board with a missing/depleted backup battery for GSC, the
+	 * board may be ready to probe the GSC before its firmware is
+	 * running.  We will wait here indefinately for the GSC/EEPROM.
+	 */
+	while (1) {
+		/* probe device */
+		dev = gsc_get_dev(1, GSC_SC_ADDR);
+		if (dev)
+			break;
+		mdelay(1);
+	}
+
+	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+	if (ret) {
+		puts("ERROR: Failed reading GSC\n");
+		return ret;
+	}
+	gsc_read();
+
+	/* banner */
+	if (!quiet) {
+		printf("GSC     : v%d 0x%04x", buf[GSC_SC_FWVER],
+		       buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
+		printf(" RST:%s", gsc_get_rst_cause(dev));
+		printf("\n");
+		gsc_info(1);
+	}
+
+	if (ret)
+		hang();
+
+	return ((16 << som_info.sdram_size) / 1024);
+}
+
+const char *gsc_get_model(void)
+{
+	return venice_model;
+}
+
+#if !(IS_ENABLED(CONFIG_SPL_BUILD))
+static int gsc_sleep(unsigned long secs)
+{
+	unsigned char reg;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_SC_ADDR);
+	if (!dev)
+		return -ENODEV;
+
+	printf("GSC Sleeping for %ld seconds\n", secs);
+	reg = (secs >> 24) & 0xff;
+	ret = dm_i2c_write(dev, 9, &reg, 1);
+	if (ret)
+		goto err;
+	reg = (secs >> 16) & 0xff;
+	ret = dm_i2c_write(dev, 8, &reg, 1);
+	if (ret)
+		goto err;
+	reg = (secs >> 8) & 0xff;
+	ret = dm_i2c_write(dev, 7, &reg, 1);
+	if (ret)
+		goto err;
+	reg = secs & 0xff;
+	ret = dm_i2c_write(dev, 6, &reg, 1);
+	if (ret)
+		goto err;
+	ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg |= (1 << 2);
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg &= ~(1 << 2);
+	reg |= 0x3;
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	printf("i2c error\n");
+	return ret;
+}
+
+static int gsc_boot_wd_disable(void)
+{
+	u8 reg;
+	struct udevice *dev;
+	int ret;
+
+	/* probe device */
+	dev = gsc_get_dev(1, GSC_SC_ADDR);
+	if (!dev)
+		return -ENODEV;
+
+	ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	reg |= (1 << GSC_SC_CTRL1_WDDIS);
+	reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK);
+	ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+	if (ret)
+		goto err;
+	puts("GSC     : boot watchdog disabled\n");
+
+	return 0;
+
+err:
+	printf("i2c error");
+	return ret;
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return gsc_info(2);
+
+	if (strcasecmp(argv[1], "sleep") == 0) {
+		if (argc < 3)
+			return CMD_RET_USAGE;
+		if (!gsc_sleep(simple_strtoul(argv[2], NULL, 10)))
+			return CMD_RET_SUCCESS;
+	} else if (strcasecmp(argv[1], "hwmon") == 0) {
+		if (!gsc_hwmon())
+			return CMD_RET_SUCCESS;
+	} else if (strcasecmp(argv[1], "wd-disable") == 0) {
+		if (!gsc_boot_wd_disable())
+			return CMD_RET_SUCCESS;
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
+	   "[sleep <secs>]|[hwmon]|[wd-disable]\n");
+#endif

board/gateworks/venice/gsc.h

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+/* I2C slave addresses */
+#define GSC_SC_ADDR             0x20
+#define GSC_RTC_ADDR            0x68
+#define GSC_HWMON_ADDR          0x29
+#define GSC_EEPROM_ADDR         0x51
+
+struct venice_board_info {
+	u8 mac[6];		/* 0x00: MAC base */
+	char equiv_dts[16];	/* 0x06: equivalent device-tree */
+	u8 res0[2];	/* 0x16: reserved */
+	u32 serial;	/* 0x18: Serial Number */
+	u8 res1[4];	/* 0x1C: reserved */
+	u8 mfgdate[4];	/* 0x20: MFG date */
+	u8 macno;		/* 0x24: number of mac addrs */
+	u8 res2[6];	/* 0x25 */
+	u8 sdram_size;	/* 0x2B: (16 << n) MB */
+	u8 sdram_speed;	/* 0x2C: (33.333 * n) MHz */
+	u8 sdram_width;	/* 0x2D: (8 << n) bit */
+	u8 res3[2];	/* 0x2E */
+	char model[16];		/* 0x30: model string */
+	u8 res4[14];	/* 0x40 */
+	u8 chksum[2];	/* 0x4E */
+};
+
+int gsc_init(int quiet);
+int gsc_hwmon(void);
+const char *gsc_get_model(void);
+const char *gsc_get_dtb_name(int level, char *buf, int len);
+int gsc_getmac(int index, uint8_t *enetaddr);
+
+#endif

board/gateworks/venice/imx8mm_venice.c

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <init.h>
+#include <led.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+	if (ddr_size == 0x4) {
+		*size = 0x100000000;
+	} else if (ddr_size == 0x3) {
+		*size = 0xc0000000;
+	} else if (ddr_size == 0x2) {
+		*size = 0x80000000;
+	} else if (ddr_size == 0x1) {
+		*size = 0x40000000;
+	} else {
+		printf("Unknown DDR type!!!\n");
+		*size = 0x40000000;
+	}
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int i  = 0;
+	const char *dtb;
+	char buf[32];
+
+	do {
+		dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
+		if (!strcmp(dtb, name))
+			return 0;
+	} while (dtb);
+
+	return -1;
+}
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	switch (phydev->phy_id) {
+	case 0x2000a231: /* TI DP83867 GbE PHY */
+		puts("DP83867 ");
+		/* LED configuration */
+		val = 0;
+		val |= 0x5 << 4; /* LED1(Amber;Speed)   : 1000BT link */
+		val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
+		phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
+		break;
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif // IS_ENABLED(CONFIG_FEC_MXC)
+
+int board_init(void)
+{
+	gsc_init(1);
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	gsc_hwmon();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	const char *ethmac;
+	char env[32];
+	int ret, i;
+	u8 enetaddr[6];
+
+	led_default_state();
+
+	/* Set mac addrs */
+	i = 0;
+	do {
+		if (i)
+			sprintf(env, "eth%daddr", i);
+		else
+			sprintf(env, "ethaddr");
+		ethmac = env_get(env);
+		if (!ethmac) {
+			ret = gsc_getmac(i, enetaddr);
+			if (!ret)
+				eth_env_set_enetaddr(env, enetaddr);
+		}
+		i++;
+	} while (!ret);
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}

board/gateworks/venice/lpddr4_timing.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+#endif /* __LPDDR4_TIMING_H__ */

board/gateworks/venice/spl.c

@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+#include <asm-generic/gpio.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/mp5416.h>
+
+#include "gsc.h"
+#include "lpddr4_timing.h"
+
+#define PCIE_RSTN IMX_GPIO_NR(4, 6)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(int size)
+{
+	struct dram_timing_info *dram_timing;
+
+	switch (size) {
+	case 1:
+		dram_timing = &dram_timing_1gb;
+		break;
+	case 4:
+		dram_timing = &dram_timing_4gb;
+		break;
+	default:
+		printf("Unknown DDR configuration: %d GiB\n", size);
+		dram_timing = &dram_timing_1gb;
+		size = 1;
+	}
+
+	printf("DRAM    : LPDDR4 %d GiB\n", size);
+	ddr_init(dram_timing);
+	writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+/*
+ * Model specific PMIC adjustments necessary prior to DRAM init
+ *
+ * Note that we can not use pmic dm drivers here as we have a generic
+ * venice dt that does not have board-specific pmic's defined.
+ *
+ * Instead we must use dm_i2c.
+ */
+static int power_init_board(void)
+{
+	const char *model = gsc_get_model();
+	struct udevice *bus;
+	struct udevice *dev;
+	int ret;
+
+	if ((!strncmp(model, "GW71", 4)) ||
+	    (!strncmp(model, "GW72", 4)) ||
+	    (!strncmp(model, "GW73", 4))) {
+		ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
+		if (ret) {
+			printf("PMIC    : failed I2C1 probe: %d\n", ret);
+			return ret;
+		}
+		ret = dm_i2c_probe(bus, 0x69, 0, &dev);
+		if (ret) {
+			printf("PMIC    : failed probe: %d\n", ret);
+			return ret;
+		}
+		puts("PMIC    : MP5416\n");
+
+		/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
+		dm_i2c_reg_write(dev, MP5416_VSET_SW3,
+				 BIT(7) | MP5416_VSET_SW3_SVAL(920000));
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+	int dram_sz;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
+	gpio_request(PCIE_RSTN, "perst#");
+	gpio_direction_output(PCIE_RSTN, 0);
+
+	/* GSC */
+	dram_sz = gsc_init(0);
+
+	/* PMIC */
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init(dram_sz);
+
+	board_init_r(NULL, 0);
+}
+
+/* determine prioritized order of boot devices to load U-Boot from */
+void board_boot_order(u32 *spl_boot_list)
+{
+	/*
+	 * If the SPL was loaded via serial loader, we try to get
+	 * U-Boot proper via USB SDP.
+	 */
+	if (spl_boot_device() == BOOT_DEVICE_BOARD)
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+
+	/* we have only eMMC in default venice dt */
+	spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/* return boot device based on where the SPL was loaded from */
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	/* SDHC2 */
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	/* SDHC3 */
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}