leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: dts: zynq: add NAND flash controller node

Browse Source 
Recently, a driver for the ARM Primecell PL35x static memory controller
(including NAND controller) was added in linux. Add the corresponding
device tree node.

Also update cfi-flash registers and location in DT.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210616155437.27378-3-michael@walle.cc
Link: https://lore.kernel.org/r/ee81d3846a1ce93f240d61537d404796e5599c1c.1645625433.git.michal.simek@xilinx.com
This commit is contained in:
Michael Walle 2022-02-23 15:10:34 +01:00 committed by Michal Simek
parent c2b74edf15
commit 03a8e826e0
3 changed files with 32 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/bitmain-antminer-s9.dts
View File

@ -50,7 +50,7 @@
ps-clk-frequency = <33333333>;
};
&nand0 {
&nfc0 {
status = "okay";
};

57
arch/arm/dts/zynq-7000.dtsi
View File

@ -246,33 +246,6 @@
#size-cells = <0>;
};
smcc: memory-controller@e000e000 {
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
interrupt-parent = <&intc>;
interrupts = <0 18 4>;
ranges ;
reg = <0xe000e000 0x1000>;
nand0: flash@e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
};
nor0: flash@e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
@ -295,6 +268,36 @@
#size-cells = <0>;
};
smcc: memory-controller@e000e000 {
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x0001000>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 18 4>;
nfc0: nand-controller@0,0 {
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
sdhci0: mmc@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";

2
arch/arm/dts/zynq-zc770-xm011.dts
View File

@ -47,7 +47,7 @@
};
};
&nand0 {
&nfc0 {
status = "okay";
};