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[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board

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This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2007-01-05 10:38:05 +01:00
parent 92eb729bad
commit 0238898382
6 changed files with 872 additions and 14 deletions
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3
cpu/ppc4xx/cpu_init.c
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@@ -31,9 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap