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Merge branch '2020-05-19-misc-fixes'

Browse Source 
- Assorted minor fixes
This commit is contained in:
Tom Rini 2020-05-20 08:22:17 -04:00
commit 023329284d
22 changed files with 113 additions and 404 deletions
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4
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -106,10 +106,6 @@ config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
select VENDOR_KM
config TARGET_SUVD3
bool "Support suvd3"
select VENDOR_KM
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM

24
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -127,16 +127,10 @@ int checkcpu(void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong msr;
#ifndef MPC83xx_RESET
ulong addr;
#endif
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
puts("Resetting the board.\n");
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
msr = mfmsr();
msr &= ~(MSR_EE | MSR_IR | MSR_DR);
@ -156,24 +150,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
/* perform reset, only one bit */
immap->reset.rcr = RCR_SWHR;
#else /* ! MPC83xx_RESET */
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */
msr = mfmsr();
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
mtmsr(msr);
/*
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
addr = CONFIG_SYS_RESET_ADDRESS;
((void (*)(void)) addr) ();
#endif /* MPC83xx_RESET */
return 1;
}
#endif

19
board/keymile/km83xx/Kconfig
View File

@ -57,25 +57,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
endif
if TARGET_SUVD3
config SYS_BOARD
default "km83xx"
config SYS_VENDOR
default "keymile"
config SYS_CONFIG_NAME
default "suvd3"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_MPC832X
imply CMD_CRAMFS
imply FS_CRAMFS
endif
if TARGET_TUXX1
config SYS_BOARD

2
board/keymile/km83xx/MAINTAINERS
View File

@ -8,9 +8,7 @@ F: configs/kmeter1_defconfig
F: include/configs/tuxx1.h
F: configs/kmopti2_defconfig
F: configs/kmtepr2_defconfig
F: include/configs/suvd3.h
F: configs/kmtegr1_defconfig
F: configs/suvd3_defconfig
F: configs/tuge1_defconfig
F: configs/tuxx1_defconfig

32
board/keymile/km83xx/km83xx.c
View File

@ -100,27 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 0, 0, 0, QE_IOP_TAB_END},
};
#if defined(CONFIG_SUVD3)
const uint upma_table[] = {
0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
};
#endif
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =
@ -138,11 +117,6 @@ int board_early_init_r(void)
{
struct km_bec_fpga *base =
(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
#if defined(CONFIG_SUVD3)
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
fsl_lbc_t *lbc = &immap->im_lbc;
u32 *mxmr = &lbc->mamr;
#endif
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
@ -178,12 +152,6 @@ int board_early_init_r(void)
/* enable Application Buffer */
setbits_8(&base->oprtl, OPRTL_XBUFENA);
#if defined(CONFIG_SUVD3)
/* configure UPMA for APP1 */
upmconfig(UPMA, (uint *) upma_table,
sizeof(upma_table) / sizeof(uint));
out_be32(mxmr, CONFIG_SYS_MAMR);
#endif
return 0;
}

3
cmd/avb.c
View File

@ -316,6 +316,9 @@ int do_avb_verify_part(struct cmd_tbl *cmdtp, int flag,
printf("Unknown error occurred\n");
}
if (out_data)
avb_slot_verify_data_free(out_data);
return res;
}

184
configs/suvd3_defconfig
View File

@ -1,184 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_SUVD3=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="IMMR"
CONFIG_BAT1_BASE=0xE0000000
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="KMBEC_FPGA"
CONFIG_BAT2_BASE=0xE8000000
CONFIG_BAT2_LENGTH_128_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="FLASH"
CONFIG_BAT3_BASE=0xF0000000
CONFIG_BAT3_LENGTH_256_MBYTES=y
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT3_DCACHE_INHIBITED=y
CONFIG_BAT3_DCACHE_GUARDED=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_BAT4=y
CONFIG_BAT4_NAME="STACK_IN_DCACHE"
CONFIG_BAT4_BASE=0xE6000000
CONFIG_BAT4_ACCESS_RW=y
CONFIG_BAT4_USER_MODE_VALID=y
CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="APP1"
CONFIG_BAT5_BASE=0xA0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="APP2"
CONFIG_BAT6_BASE=0xB0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_INHIBITED=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xF0000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_256_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE8000000
CONFIG_LBLAW1_NAME="KMBEC_FPGA"
CONFIG_LBLAW1_LENGTH_128_MBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xA0000000
CONFIG_LBLAW2_NAME="APP1"
CONFIG_LBLAW2_LENGTH_256_MBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xB0000000
CONFIG_LBLAW3_NAME="APP2"
CONFIG_LBLAW3_LENGTH_256_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xF0000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_256_MBYTES=y
CONFIG_OR0_SCY_5=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
CONFIG_BR1_OR1_BASE=0xE8000000
CONFIG_OR1_AM_128_MBYTES=y
CONFIG_OR1_SCY_2=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="APP1"
CONFIG_BR2_OR2_BASE=0xA0000000
CONFIG_BR2_PORTSIZE_16BIT=y
CONFIG_BR2_MACHINE_UPMA=y
CONFIG_OR2_AM_256_MBYTES=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="APP2"
CONFIG_BR3_OR3_BASE=0xB0000000
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_256_MBYTES=y
CONFIG_OR3_SCY_3=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_IMLS=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
# CONFIG_PCI is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

1
drivers/crypto/rsa_mod_exp/mod_exp_sw.c
View File

@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = {
.name = "mod_exp_sw",
.id = UCLASS_MOD_EXP,
.ops = &mod_exp_ops_sw,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(mod_exp_sw) = {

34
include/configs/suvd3.h
View File

@ -1,34 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_HOSTNAME "suvd3"
/* include common defines/options for all Keymile boards */
#include "km/keymile-common.h"
#include "km/km-powerpc.h"
#include "km/km-mpc83xx.h"
#include "km/km-mpc832x.h"
#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
0x0000c000 | \
MxMR_WLFx_2X)
#endif /* __CONFIG_H */

5
include/mpc83xx.h
View File

@ -12,11 +12,6 @@
#include <asm/e300.h>
#endif
/*
* MPC83xx cpu provide RCR register to do reset thing specially
*/
#define MPC83xx_RESET
/*
* System reset offset (PowerPC standard)
*/

1
scripts/config_whitelist.txt
View File

@ -1733,7 +1733,6 @@ CONFIG_STV0991_HZ
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
CONFIG_SUNXI_MAX_FB_SIZE
CONFIG_SUVD3
CONFIG_SXNI855T
CONFIG_SYSFLAGS_ADDR
CONFIG_SYSFS

8
test/compression.c
View File

@ -164,7 +164,7 @@ static int compress_using_bzip2(struct unit_test_state *uts,
{
/* There is no bzip2 compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
ut_asserteq(0, memcmp(plain, in, in_size));
ut_asserteq_mem(plain, in, in_size);
if (bzip2_compressed_size > out_max)
return -1;
@ -199,7 +199,7 @@ static int compress_using_lzma(struct unit_test_state *uts,
{
/* There is no lzma compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
ut_asserteq(0, memcmp(plain, in, in_size));
ut_asserteq_mem(plain, in, in_size);
if (lzma_compressed_size > out_max)
return -1;
@ -233,7 +233,7 @@ static int compress_using_lzo(struct unit_test_state *uts,
{
/* There is no lzo compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
ut_asserteq(0, memcmp(plain, in, in_size));
ut_asserteq_mem(plain, in, in_size);
if (lzo_compressed_size > out_max)
return -1;
@ -268,7 +268,7 @@ static int compress_using_lz4(struct unit_test_state *uts,
{
/* There is no lz4 compression in u-boot, so fake it. */
ut_asserteq(in_size, strlen(plain));
ut_asserteq(0, memcmp(plain, in, in_size));
ut_asserteq_mem(plain, in, in_size);
if (lz4_compressed_size > out_max)
return -1;

6
test/dm/acpi.c
View File

@ -218,20 +218,20 @@ static int dm_test_acpi_setup_base_tables(struct unit_test_state *uts)
rsdp = buf + 16;
ut_asserteq_ptr(rsdp, ctx.rsdp);
ut_assertok(memcmp(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature)));
ut_asserteq_mem(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature));
ut_asserteq(sizeof(*rsdp), rsdp->length);
ut_assertok(table_compute_checksum(rsdp, 20));
ut_assertok(table_compute_checksum(rsdp, sizeof(*rsdp)));
rsdt = PTR_ALIGN((void *)rsdp + sizeof(*rsdp), 16);
ut_asserteq_ptr(rsdt, ctx.rsdt);
ut_assertok(memcmp("RSDT", rsdt->header.signature, ACPI_NAME_LEN));
ut_asserteq_mem("RSDT", rsdt->header.signature, ACPI_NAME_LEN);
ut_asserteq(sizeof(*rsdt), rsdt->header.length);
ut_assertok(table_compute_checksum(rsdt, sizeof(*rsdt)));
xsdt = PTR_ALIGN((void *)rsdt + sizeof(*rsdt), 16);
ut_asserteq_ptr(xsdt, ctx.xsdt);
ut_assertok(memcmp("XSDT", xsdt->header.signature, ACPI_NAME_LEN));
ut_asserteq_mem("XSDT", xsdt->header.signature, ACPI_NAME_LEN);
ut_asserteq(sizeof(*xsdt), xsdt->header.length);
ut_assertok(table_compute_checksum(xsdt, sizeof(*xsdt)));

4
test/dm/axi.c
View File

@ -66,11 +66,11 @@ static int dm_test_axi_store(struct unit_test_state *uts)
/* Test writing */
val = 0x55667788;
axi_write(store, 0, &val, AXI_SIZE_32);
ut_asserteq(0, memcmp(data, tdata1, ARRAY_SIZE(tdata1)));
ut_asserteq_mem(data, tdata1, ARRAY_SIZE(tdata1));
val = 0xaabbccdd;
axi_write(store, 3, &val, AXI_SIZE_32);
ut_asserteq(0, memcmp(data + 3, tdata2, ARRAY_SIZE(tdata1)));
ut_asserteq_mem(data + 3, tdata2, ARRAY_SIZE(tdata1));
return 0;
}

6
test/dm/dma.c
View File

@ -30,8 +30,8 @@ static int dm_test_dma_m2m(struct unit_test_state *uts)
src_buf[i] = i;
ut_assertok(dma_memcpy(dst_buf, src_buf, len));
ut_asserteq_mem(src_buf, dst_buf, len);
ut_assertok(memcmp(src_buf, dst_buf, len));
return 0;
}
DM_TEST(dm_test_dma_m2m, DM_TESTF_SCAN_FDT);
@ -72,7 +72,7 @@ static int dm_test_dma(struct unit_test_state *uts)
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
ut_assertok(memcmp(src_buf, dst_buf, len));
ut_asserteq_mem(src_buf, dst_buf, len);
return 0;
}
@ -117,7 +117,7 @@ static int dm_test_dma_rx(struct unit_test_state *uts)
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
ut_assertok(memcmp(src_buf, dst_buf, len));
ut_asserteq_mem(src_buf, dst_buf, len);
return 0;
}

12
test/dm/eth.c
View File

@ -282,17 +282,17 @@ static int sb_check_arp_reply(struct udevice *dev, void *packet,
ut_assert(arp_is_waiting());
/* Validate response */
ut_assert(memcmp(eth->et_src, net_ethaddr, ARP_HLEN) == 0);
ut_assert(memcmp(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN) == 0);
ut_asserteq_mem(eth->et_src, net_ethaddr, ARP_HLEN);
ut_asserteq_mem(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(eth->et_protlen == htons(PROT_ARP));
ut_assert(arp->ar_hrd == htons(ARP_ETHER));
ut_assert(arp->ar_pro == htons(PROT_IP));
ut_assert(arp->ar_hln == ARP_HLEN);
ut_assert(arp->ar_pln == ARP_PLEN);
ut_assert(memcmp(&arp->ar_sha, net_ethaddr, ARP_HLEN) == 0);
ut_asserteq_mem(&arp->ar_sha, net_ethaddr, ARP_HLEN);
ut_assert(net_read_ip(&arp->ar_spa).s_addr == net_ip.s_addr);
ut_assert(memcmp(&arp->ar_tha, priv->fake_host_hwaddr, ARP_HLEN) == 0);
ut_asserteq_mem(&arp->ar_tha, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(net_read_ip(&arp->ar_tpa).s_addr ==
string_to_ip("1.1.2.4").s_addr);
@ -373,8 +373,8 @@ static int sb_check_ping_reply(struct udevice *dev, void *packet,
ut_assert(arp_is_waiting());
/* Validate response */
ut_assert(memcmp(eth->et_src, net_ethaddr, ARP_HLEN) == 0);
ut_assert(memcmp(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN) == 0);
ut_asserteq_mem(eth->et_src, net_ethaddr, ARP_HLEN);
ut_asserteq_mem(eth->et_dest, priv->fake_host_hwaddr, ARP_HLEN);
ut_assert(eth->et_protlen == htons(PROT_IP));
ut_assert(net_read_ip(&ip->ip_src).s_addr == net_ip.s_addr);

18
test/dm/i2c.c
View File

@ -51,10 +51,10 @@ static int dm_test_i2c_read_write(struct unit_test_state *uts)
ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0AB\0", sizeof(buf));
return 0;
}
@ -123,7 +123,7 @@ static int dm_test_i2c_bytewise(struct unit_test_state *uts)
ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
/* Tell the EEPROM to only read/write one register at a time */
ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
@ -132,34 +132,34 @@ static int dm_test_i2c_bytewise(struct unit_test_state *uts)
/* Now we only get the first byte - the rest will be 0xff */
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
/* If we do a separate transaction for each byte, it works */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
/* This will only write A */
ut_assertok(i2c_set_chip_flags(dev, 0));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
/* Check that the B was ignored */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0A\0\0\0", sizeof(buf));
/* Now write it again with the new flags, it should work */
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
DM_I2C_CHIP_RD_ADDRESS));
ut_assertok(dm_i2c_read(dev, 0, buf, 5));
ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf)));
ut_asserteq_mem(buf, "\0\0AB\0\0", sizeof(buf));
/* Restore defaults */
sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);

10
test/dm/misc.c
View File

@ -25,24 +25,24 @@ static int dm_test_misc(struct unit_test_state *uts)
ut_asserteq(5, misc_write(dev, 4, "WRITE", 5));
ut_asserteq(9, misc_read(dev, 0, buf, 9));
ut_assertok(memcmp(buf, "TESTWRITE", 9));
ut_asserteq_mem(buf, "TESTWRITE", 9);
/* Call tests */
id = 0;
ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
ut_assertok(memcmp(buf, "Zero", 4));
ut_asserteq_mem(buf, "Zero", 4);
id = 2;
ut_assertok(misc_call(dev, 0, &id, 4, buf, 16));
ut_assertok(memcmp(buf, "Two", 3));
ut_asserteq_mem(buf, "Two", 3);
ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
ut_assertok(memcmp(buf, "Forty-two", 9));
ut_asserteq_mem(buf, "Forty-two", 9);
id = 1;
ut_assertok(misc_call(dev, 1, &id, 4, buf, 16));
ut_assertok(memcmp(buf, "Forty-one", 9));
ut_asserteq_mem(buf, "Forty-one", 9);
/* IOCTL tests */

128
test/dm/osd.c
View File

@ -71,27 +71,29 @@ static int dm_test_osd_basics(struct unit_test_state *uts)
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
ut_assertok(memcmp(text, " "
" "
" "
" "
" "
" "
" "
" "
" "
" ", memsize / 2));
ut_asserteq_mem(text,
" "
" "
" "
" "
" "
" "
" "
" "
" "
" ", memsize / 2);
ut_assertok(memcmp(colors, "kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk", memsize / 2));
ut_asserteq_mem(colors,
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk", memsize / 2);
print_mem(mem, 10, 10);
@ -100,27 +102,29 @@ static int dm_test_osd_basics(struct unit_test_state *uts)
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
ut_assertok(memcmp(text, " "
" Blah "
" "
" "
" "
" "
" "
" "
" "
" ", memsize / 2));
ut_asserteq_mem(text,
" "
" Blah "
" "
" "
" "
" "
" "
" "
" "
" ", memsize / 2);
ut_assertok(memcmp(colors, "kkkkkkkkkk"
"krrrrkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk", memsize / 2));
ut_asserteq_mem(colors,
"kkkkkkkkkk"
"krrrrkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk"
"kkkkkkkkkk", memsize / 2);
print_mem(mem, 10, 10);
@ -152,17 +156,19 @@ static int dm_test_osd_extended(struct unit_test_state *uts)
ut_assertok(sandbox_osd_get_mem(dev, mem, memsize));
split(mem, memsize / 2, text, colors);
ut_assertok(memcmp(text, " "
" "
" "
" "
" ", memsize / 2));
ut_asserteq_mem(text,
" "
" "
" "
" "
" ", memsize / 2);
ut_assertok(memcmp(colors, "kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk", memsize / 2));
ut_asserteq_mem(colors,
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk"
"kkkkkkkkkkkkkkkkkkkk", memsize / 2);
print_mem(mem, 20, 5);
@ -192,17 +198,19 @@ static int dm_test_osd_extended(struct unit_test_state *uts)
print_mem(mem, 20, 5);
ut_assertok(memcmp(text, "+---- OSD menu ----+"
"| * Entry 1 |"
"| (*) Entry 2 |"
"| * Entry 3 |"
"+------------------+", memsize / 2));
ut_asserteq_mem(text,
"+---- OSD menu ----+"
"| * Entry 1 |"
"| (*) Entry 2 |"
"| * Entry 3 |"
"+------------------+", memsize / 2);
ut_assertok(memcmp(colors, "gggggggggggggggggggg"
"gkbbbbbbbbbbbkkkkkkg"
"gkbbbbbbbbbbbkkkkkkg"
"gkbbbbbbbbbbbkkkkkkg"
"gggggggggggggggggggg", memsize / 2));
ut_asserteq_mem(colors,
"gggggggggggggggggggg"
"gkbbbbbbbbbbbkkkkkkg"
"gkbbbbbbbbbbbkkkkkkg"
"gkbbbbbbbbbbbkkkkkkg"
"gggggggggggggggggggg", memsize / 2);
return 0;
}

6
test/dm/remoteproc.c
View File

@ -223,7 +223,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts)
/* Load firmware in loaded_firmware, and verify it */
ut_assertok(rproc_elf32_load_image(dev, (ulong)valid_elf32, size));
ut_assertok(memcmp(loaded_firmware, valid_elf32, loaded_firmware_size));
ut_asserteq_mem(loaded_firmware, valid_elf32, loaded_firmware_size);
ut_asserteq(rproc_elf_get_boot_addr(dev, (unsigned long)valid_elf32),
0x08000000);
unmap_physmem(loaded_firmware, MAP_NOCACHE);
@ -243,8 +243,8 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts)
&rsc_addr, &rsc_size));
ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE);
ut_asserteq(rsc_size, rsc_table_size);
ut_assertok(memcmp(loaded_firmware, valid_elf32 + shdr->sh_offset,
shdr->sh_size));
ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset,
shdr->sh_size);
unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Invalid ELF Magic */

4
test/dm/sf.c
View File

@ -35,7 +35,7 @@ static int dm_test_spi_flash(struct unit_test_state *uts)
dst = map_sysmem(0x20000 + full_size, full_size);
ut_assertok(spi_flash_read_dm(dev, 0, size, dst));
ut_assertok(memcmp(src, dst, size));
ut_asserteq_mem(src, dst, size);
/* Erase */
ut_assertok(spi_flash_erase_dm(dev, 0, size));
@ -48,7 +48,7 @@ static int dm_test_spi_flash(struct unit_test_state *uts)
src[i] = i;
ut_assertok(spi_flash_write_dm(dev, 0, size, src));
ut_assertok(spi_flash_read_dm(dev, 0, size, dst));
ut_assertok(memcmp(src, dst, size));
ut_asserteq_mem(src, dst, size);
/* Try the write-protect stuff */
ut_assertok(uclass_first_device_err(UCLASS_SPI_EMUL, &emul));

6
test/unicode_ut.c
View File

@ -67,8 +67,9 @@ static int unicode_test_u16_strdup(struct unit_test_state *uts)
u16 *copy = u16_strdup(c4);
ut_assert(copy != c4);
ut_assert(!memcmp(copy, c4, sizeof(c4)));
ut_asserteq_mem(copy, c4, sizeof(c4));
free(copy);
return 0;
}
UNICODE_TEST(unicode_test_u16_strdup);
@ -80,7 +81,8 @@ static int unicode_test_u16_strcpy(struct unit_test_state *uts)
r = u16_strcpy(copy, c1);
ut_assert(r == copy);
ut_assert(!memcmp(copy, c1, sizeof(c1)));
ut_asserteq_mem(copy, c1, sizeof(c1));
return 0;
}
UNICODE_TEST(unicode_test_u16_strcpy);