pm9263: use macro instead of hardcode value for the lowlevel_init
optimize a few the RAM init Signed-off-by: Ilko Iliev <iliev@ronetix.at> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
7a11c7f974
commit
01550a2b65
@ -87,7 +87,7 @@ POS1:
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*/
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ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
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ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
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ldr r0, =0x0000FF01
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ldr r0, =CONFIG_SYS_MOR_VAL
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str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
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/* Reading the PMC Status to detect when the Main Oscillator is enabled */
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@ -239,7 +239,7 @@ static int pm9263_lcd_hw_psram_init(void)
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at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
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(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
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AT91_MATRIX_DEFMSTR_TYPE_FIXED |
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(AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
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(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
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return 0;
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}
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@ -65,6 +65,7 @@
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#define AT91_PMC_USBDIV_2 (1 << 28)
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#define AT91_PMC_USBDIV_4 (2 << 28)
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
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@ -32,8 +32,8 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define MASTER_PLL_DIV 15
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#define MASTER_PLL_MUL 162
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#define MASTER_PLL_DIV 6
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#define MASTER_PLL_MUL 65
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#define MAIN_PLL_DIV 2 /* 2 or 4 */
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#define AT91_MAIN_CLOCK 18432000
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@ -46,39 +46,76 @@
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* clocks */
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#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
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#define CONFIG_SYS_PLLAR_VAL \
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(0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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AT91_PMC_PLLCOUNT | /* PLL Counter */ \
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(2 << 28) | /* PLL Clock Frequency Range */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#if (MAIN_PLL_DIV == 2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL 0x00000100
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL 0x00000102
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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#else
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL 0x00000200
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91RM9200_PMC_MDIV_3 | \
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AT91_PMC_PDIV_1)
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL 0x00000202
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91RM9200_PMC_MDIV_3 | \
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AT91_PMC_PDIV_1)
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#endif
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
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#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
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(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
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AT91_MATRIX_EBI0_CS1A_SDRAMC)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 0
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
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#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
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#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
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/* SDRAMC_CR - Configuration register*/
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#define CONFIG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* tWR - Write Recovery Delay */ \
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(7 << 12) | /* tRC - Row Cycle Delay */ \
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(2 << 16) | /* tRP - Row Precharge Delay */ \
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(2 << 20) | /* tRCD - Row to Column Delay */ \
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(5 << 24) | /* tRAS - Active to Precharge Delay */ \
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(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL 0
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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@ -87,25 +124,41 @@
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
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#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
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#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
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#define CONFIG_SYS_SMC0_MODE0_VAL 0x00161003 /* SMC_MODE */
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
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AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
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AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
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AT91_SMC_DBW_16 | \
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AT91_SMC_TDFMODE | \
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AT91_SMC_TDF_(6))
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#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_PROCRST | \
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AT91_RSTC_RSTTYP_WAKEUP | \
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AT91_RSTC_RSTTYP_WATCHDOG)
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/* Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
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/* */
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
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AT91_WDT_WDV | \
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AT91_WDT_WDDIS | \
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AT91_WDT_WDD)
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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