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MPC8548: dts: Added PCIe DT node

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MPC8548 integrated a PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for the PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-08-27 11:05:23 +00:00 committed by Prabhakar Kushwaha
parent 92e025c6e1
commit 00acf26044
3 changed files with 21 additions and 0 deletions
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9
arch/powerpc/dts/mpc8548-post.dtsi
View File

@ -25,3 +25,12 @@
last-interrupt-source = <255>; last-interrupt-source = <255>;
}; };
}; };
&pcie {
compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

6
arch/powerpc/dts/mpc8548cds.dts
View File

@ -18,6 +18,12 @@
soc: soc8548@e0000000 { soc: soc8548@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>; ranges = <0x0 0x0 0xe0000000 0x100000>;
}; };
pcie: pcie@e000a000 {
reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
}; };
/include/ "mpc8548-post.dtsi" /include/ "mpc8548-post.dtsi"

6
arch/powerpc/dts/mpc8548cds_36b.dts
View File

@ -18,6 +18,12 @@
soc: soc8548@fe0000000 { soc: soc8548@fe0000000 {
ranges = <0x0 0xf 0xe0000000 0x100000>; ranges = <0x0 0xf 0xe0000000 0x100000>;
}; };
pcie: pcie@fe000a000 {
reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
}; };
/include/ "mpc8548-post.dtsi" /include/ "mpc8548-post.dtsi"