ARM: uniphier: remove sLD3 SoC support

This SoC is too old.  It is difficult to maintain any longer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
2017-08-13 09:01:13 +09:00
parent 213fcabdfd
commit 00aa453ebf
44 changed files with 30 additions and 1105 deletions

View File

@@ -146,10 +146,6 @@ static int uniphier_clk_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_clk_match[] = {
{
.compatible = "socionext,uniphier-sld3-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
{
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,

View File

@@ -64,11 +64,9 @@ static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
UNIPHIER_MIO_CLK_USB2(8, 0),
UNIPHIER_MIO_CLK_USB2(9, 1),
UNIPHIER_MIO_CLK_USB2(10, 2),
UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
UNIPHIER_CLK_END
};

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@@ -3,12 +3,6 @@ if ARCH_UNIPHIER
config PINCTRL_UNIPHIER
bool
config PINCTRL_UNIPHIER_SLD3
bool "UniPhier sLD3 SoC pinctrl driver"
depends on ARCH_UNIPHIER_SLD3
default y
select PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_LD4
bool "UniPhier LD4 SoC pinctrl driver"
depends on ARCH_UNIPHIER_LD4

View File

@@ -4,7 +4,6 @@
obj-y += pinctrl-uniphier-core.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o

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@@ -1,129 +0,0 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include "pinctrl-uniphier.h"
static const unsigned emmc_pins[] = {55, 56, 60};
static const int emmc_muxvals[] = {1, 1, 1};
static const unsigned emmc_dat8_pins[] = {57};
static const int emmc_dat8_muxvals[] = {1};
static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
113};
static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
static const unsigned ether_rmii_pins[] = {35};
static const int ether_rmii_muxvals[] = {1};
static const unsigned i2c0_pins[] = {36};
static const int i2c0_muxvals[] = {0};
static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
static const int nand_muxvals[] = {1, 1, 1, 1, 1};
static const unsigned nand_cs1_pins[] = {41};
static const int nand_cs1_muxvals[] = {1};
static const unsigned sd_pins[] = {42, 43, 44, 45};
static const int sd_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
77, 78, 79, 80, 88, 89, 91, 92, 99};
static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1};
static const unsigned system_bus_cs0_pins[] = {93};
static const int system_bus_cs0_muxvals[] = {1};
static const unsigned system_bus_cs1_pins[] = {94};
static const int system_bus_cs1_muxvals[] = {1};
static const unsigned system_bus_cs2_pins[] = {95};
static const int system_bus_cs2_muxvals[] = {1};
static const unsigned system_bus_cs3_pins[] = {96};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned system_bus_cs4_pins[] = {81};
static const int system_bus_cs4_muxvals[] = {1};
static const unsigned system_bus_cs5_pins[] = {82};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {63, 64};
static const int uart0_muxvals[] = {0, 1};
static const unsigned uart1_pins[] = {65, 66};
static const int uart1_muxvals[] = {0, 1};
static const unsigned uart2_pins[] = {96, 102};
static const int uart2_muxvals[] = {2, 2};
static const unsigned usb0_pins[] = {13, 14};
static const int usb0_muxvals[] = {0, 1};
static const unsigned usb1_pins[] = {15, 16};
static const int usb1_muxvals[] = {0, 1};
static const unsigned usb2_pins[] = {17, 18};
static const int usb2_muxvals[] = {0, 1};
static const unsigned usb3_pins[] = {19, 20};
static const int usb3_muxvals[] = {0, 1};
static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
UNIPHIER_PINCTRL_GROUP_SPL(emmc),
UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_mii),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
UNIPHIER_PINCTRL_GROUP(usb3)
};
static const char * const uniphier_sld3_functions[] = {
UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_mii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
UNIPHIER_PINMUX_FUNCTION(usb3),
};
static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
.groups = uniphier_sld3_groups,
.groups_count = ARRAY_SIZE(uniphier_sld3_groups),
.functions = uniphier_sld3_functions,
.functions_count = ARRAY_SIZE(uniphier_sld3_functions),
.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
};
static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
{
return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
}
static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-sld3-pinctrl" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
.name = "uniphier-sld3-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
.probe = uniphier_sld3_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};

View File

@@ -56,7 +56,7 @@ struct uniphier_reset_data {
#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
UNIPHIER_RESET_END,
};
@@ -269,13 +269,9 @@ static int uniphier_reset_probe(struct udevice *dev)
static const struct udevice_id uniphier_reset_match[] = {
/* System reset */
{
.compatible = "socionext,uniphier-sld3-reset",
.data = (ulong)uniphier_sld3_sys_reset_data,
},
{
.compatible = "socionext,uniphier-ld4-reset",
.data = (ulong)uniphier_sld3_sys_reset_data,
.data = (ulong)uniphier_ld4_sys_reset_data,
},
{
.compatible = "socionext,uniphier-pro4-reset",
@@ -283,7 +279,7 @@ static const struct udevice_id uniphier_reset_match[] = {
},
{
.compatible = "socionext,uniphier-sld8-reset",
.data = (ulong)uniphier_sld3_sys_reset_data,
.data = (ulong)uniphier_ld4_sys_reset_data,
},
{
.compatible = "socionext,uniphier-pro5-reset",
@@ -302,10 +298,6 @@ static const struct udevice_id uniphier_reset_match[] = {
.data = (ulong)uniphier_ld20_sys_reset_data,
},
/* Media I/O reset */
{
.compatible = "socionext,uniphier-sld3-mio-clock",
.data = (ulong)uniphier_mio_reset_data,
},
{
.compatible = "socionext,uniphier-ld4-mio-reset",
.data = (ulong)uniphier_mio_reset_data,