u-boot-imx-20220523

------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087 Additionally to u-boot-imx20200520: - DH MX8MP - i.MX GPIO: reading GPIO when direction is output - Menlo i.MX53: switch to DM And from u-boot-imx20200520: - fix Verdin hang - add pca9450 regulator - conversion to DM_SERIAL - NAND block handling - fix crypto - enable cache on some boards - add ACC board (MX6) -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYotwGw8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76bsGgCfX5NxKe5FDWuvr3SRdt1mHJG5vMsAmwX5SxGF MjERnrOg0X/Z9984CWL2 =/WEs -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20220523 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087 Additionally to u-boot-imx20200520: - DH MX8MP - i.MX GPIO: reading GPIO when direction is output - Menlo i.MX53: switch to DM And from u-boot-imx20200520: - fix Verdin hang - add pca9450 regulator - conversion to DM_SERIAL - NAND block handling - fix crypto - enable cache on some boards - add ACC board (MX6)
2022-05-23 09:25:39 -04:00 · 2022-05-23 09:25:39 -04:00 · 004d30c786
commit 004d30c786
parent 6f00b97d7e 4d573d5c98
149 changed files with 7062 additions and 955 deletions
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@ -409,7 +409,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@ -1648,7 +1648,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
 	serdes_misc_init();

--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@ -738,6 +738,7 @@ dtb-y += \
 	imx6dl-cubox-i-emmc-som-v15.dtb \
 	imx6dl-cubox-i-som-v15.dtb \
 	imx6dl-dhcom-pdk2.dtb \
+	imx6dl-dhcom-picoitx.dts \
 	imx6dl-gw51xx.dtb \
 	imx6dl-gw52xx.dtb \
 	imx6dl-gw53xx.dtb \
@ -771,12 +772,14 @@ dtb-y += \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard-revd1.dtb \
+	imx6s-dhcom-drc02.dtb

 endif

 ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
 dtb-y += \
 	imx6-apalis.dtb \
+	imx6q-bosch-acc.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-cubox-i.dtb \
 	imx6q-cubox-i-emmc-som-v15.dtb \
@ -936,6 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mn-beacon-kit.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
+	imx8mp-dhcom-pdk2.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-venice.dtb \
--- a/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi
@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
+ */
+
+#include "imx6qdl-dhcom-u-boot.dtsi"
+
+&fec {
+	phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+};
--- a/arch/arm/dts/imx6dl-dhcom-picoitx.dts
+++ b/arch/arm/dts/imx6dl-dhcom-picoitx.dts
@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
+ * DHCOM PCB number: 493-300 or newer
+ * PicoITX PCB number: 487-600 or newer
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-picoitx.dtsi"
+
+/ {
+	model = "DH electronics i.MX6DL DHCOM on PicoITX";
+	compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
+		     "fsl,imx6dl";
+};
--- a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
+++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi
@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Copyright (C) 2022 Denx Software Engineering GmbH
+ * Philip Oberfichtner <pro@denx.de>
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		bus@2000000 {
+			u-boot,dm-spl;
+
+			spba-bus@2000000 {
+				u-boot,dm-spl;
+			};
+		};
+
+		bus@2100000 {
+			u-boot,dm-spl;
+		};
+	};
+
+	bootcount {
+		compatible = "u-boot,bootcount-pmic";
+		pmic = <&pmic>;
+	};
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc4 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&gpio6 {
+	u-boot,dm-spl;
+};
+
+&gpio7 {
+	u-boot,dm-spl;
+};
+
+&wdog1 {
+	u-boot,dm-spl;
+};
--- a/arch/arm/dts/imx6q-bosch-acc.dts
+++ b/arch/arm/dts/imx6q-bosch-acc.dts
@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for the i.MX6-based Bosch ACC board.
+ *
+ * Copyright (C) 2016 Garz & Fricke GmbH
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
+ * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
+ * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx6q.dtsi"
+
+/ {
+	model = "Bosch ACC";
+	compatible = "bosch,imx6q-acc", "fsl,imx6q";
+
+	aliases {
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		mmc0 = &usdhc4;
+		mmc1 = &usdhc2;
+		serial0 = &uart2;
+		serial1 = &uart1;
+	};
+
+	memory@10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0x40000000>;
+	};
+
+	backlight_lvds: backlight-lvds {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 200000>;
+		brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
+		num-interpolated-steps = <10>;
+		default-brightness-level = <60>;
+		power-supply = <&reg_lcd>;
+	};
+
+	panel {
+		compatible = "dataimage,fg1001l0dsswmg01";
+		backlight = <&backlight_lvds>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+
+	refclk: refclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clks IMX6QDL_CLK_CKO2>;
+		clock-div = <1>;
+		clock-mult = <1>;
+		clock-output-names = "12mhz_refclk";
+		assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
+				  <&clks IMX6QDL_CLK_CKO2>,
+				  <&clks IMX6QDL_CLK_CKO2_SEL>;
+		assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
+					 <&clks IMX6QDL_CLK_CKO2_PODF>,
+					 <&clks IMX6QDL_CLK_OSC>;
+		assigned-clock-rates = <0>, <12000000>, <0>;
+	};
+
+	cpus {
+		cpu0: cpu@0 {
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1225000
+				852000  1225000
+				792000  1150000
+				396000  950000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1225000
+				996000	1175000
+				852000	1175000
+				792000	1150000
+				396000	1150000
+			>;
+		};
+
+		cpu1: cpu@1 {
+			operating-points = <
+				/* kHz    uV */
+				1200000 1275000
+				996000  1225000
+				852000  1225000
+				792000  1150000
+				396000  950000
+			>;
+			fsl,soc-operating-points = <
+				/* ARM kHz  SOC-PU uV */
+				1200000 1225000
+				996000	1175000
+				852000	1175000
+				792000	1150000
+				396000	1150000
+			>;
+		};
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		led_red: led-0 {
+			color = <LED_COLOR_ID_RED>;
+			max-brightness = <248>;
+			default-state = "off";
+			pwms = <&pwm2 0 500000>;
+		};
+
+		led_white: led-1 {
+			color = <LED_COLOR_ID_WHITE>;
+			max-brightness = <248>;
+			default-state = "off";
+			pwms = <&pwm3 0 500000>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reset_gpio_led>;
+
+		led-2 {
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	reg_5p0: regulator-5p0 {
+		compatible = "regulator-fixed";
+		regulator-name = "5p0";
+	};
+
+	reg_vin: regulator-vin {
+		compatible = "regulator-fixed";
+		regulator-name = "VIN";
+		regulator-min-microvolt = <4500000>;
+		regulator-max-microvolt = <4500000>;
+		regulator-always-on;
+		vin-supply = <&reg_5p0>;
+	};
+
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&reg_5p0>;
+	};
+
+	reg_usb_h2_vbus: regulator-usb-h2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h2_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&reg_5p0> ;
+		regulator-always-on;
+	};
+
+	reg_vsnvs: regulator-vsnvs {
+		compatible = "regulator-fixed";
+		regulator-name = "VSNVS_3V0";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		regulator-always-on;
+		vin-supply = <&reg_5p0>;
+	};
+
+	reg_lcd: regulator-lcd {
+		compatible = "regulator-fixed";
+		regulator-name = "LCD0 POWER";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd_enable>;
+		gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
+	reg_dac: regulator-dac {
+		compatible = "regulator-fixed";
+		regulator-name = "vref_dac";
+		regulator-min-microvolt = <20000>;
+		regulator-max-microvolt = <20000>;
+		vin-supply = <&reg_5p0> ;
+		regulator-boot-on;
+	};
+
+	reg_sw4: regulator-sw4 {
+		compatible = "regulator-fixed";
+		regulator-name = "SW4_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&reg_5p0>;
+	};
+
+	reg_sys: regulator-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "SYS_4V2";
+		regulator-min-microvolt = <4200000>;
+		regulator-max-microvolt = <4200000>;
+		regulator-always-on;
+		vin-supply = <&reg_5p0>;
+	};
+};
+
+&reg_arm {
+	vin-supply = <&sw2_reg>;
+};
+
+&reg_soc {
+	vin-supply = <&sw1c_reg>;
+};
+
+&reg_vdd1p1 {
+	vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd2p5 {
+	vin-supply = <&reg_vsnvs>;
+};
+
+&reg_vdd3p0 {
+	vin-supply = <&reg_vsnvs>;
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	clocks = <&clks IMX6QDL_CLK_ENET>,
+		<&clks IMX6QDL_CLK_ENET>,
+		<&clks IMX6QDL_CLK_ENET>,
+		<&clks IMX6QDL_CLK_ENET_REF>;
+	clock-names = "ipg", "ahb", "ptp", "enet_out";
+	phy-mode = "rmii";
+	phy-supply = <&reg_sw4>;
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			interrupt-parent = <&gpio1>;
+			interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+			smsc,disable-energy-detect;
+		};
+	};
+};
+
+&gpu_vg {
+	status = "disabled";
+};
+
+&gpu_2d {
+	status = "disabled";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	pmic: pmic@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1c_reg: sw1c {
+				regulator-name = "VDD_SOC (sw1abc)";
+				regulator-min-microvolt = <1275000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-name = "VDD_ARM (sw2)";
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw3a_reg: sw3a {
+				compatible = "regulator-fixed";
+				regulator-name = "DDR_1V5a";
+				regulator-boot-on;
+				regulator-always-on;
+
+			};
+
+			sw3b_reg: sw3b {
+				compatible = "regulator-fixed";
+				regulator-name = "DDR_1V5b";
+				regulator-boot-on;
+				regulator-always-on;
+
+			};
+
+			sw4_reg: sw4 {
+				regulator-name = "AUX 3V15 (sw4)";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "disabled";
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	lm75: sensor@49 {
+		compatible = "national,lm75b";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lm75>;
+		reg = <0x49>;
+	};
+
+	eeprom: eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	rtc: rtc@51 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_rtc>;
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	eeprom_ext: eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	usb3503: usb@8 {
+		compatible = "smsc,usb3503";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb3503>;
+		reg = <0x08>;
+		connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
+		intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
+		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
+		initial-mode = <1>;
+		clocks = <&refclk>;
+		clock-names = "refclk";
+		refclk-frequency = <12000000>;
+	};
+
+	exc3000: touchscreen@2a {
+		compatible = "eeti,exc3000";
+		reg = <0x2a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ctouch>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		touchscreen-size-x = <4096>;
+		touchscreen-size-y = <4096>;
+	};
+
+	vcnl4035: light-sensor@60 {
+		compatible = "vishay,vcnl4035";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_proximity>;
+		reg = <0x60>;
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds0: lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+
+		port@4 {
+			reg = <4>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&pwm3 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+	status = "okay";
+};
+
+&pwm4 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+	linux,rs485-enabled-at-boot-time;
+	rs485-rx-during-tx;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbh2 {
+	pinctrl-names = "idle", "active";
+	pinctrl-0 = <&pinctrl_usbh2_idle>;
+	pinctrl-1 = <&pinctrl_usbh2_active>;
+	vbus-supply = <&reg_usb_h2_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	vbus-supply = <&reg_usb_otg_vbus>;
+	disable-over-current;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	voltage-ranges = <3300 3300>;
+	vmmc-supply = <&reg_sw4>;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	keep-power-in-suspend;
+	voltage-ranges = <3300 3300>;
+	vmmc-supply = <&reg_sw4>;
+	fsl,wp-controller;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog1>;
+	fsl,ext-reset-output;
+	timeout-sec=<10>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23	0x1b0b0	/* FEC INT */
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x0001b098
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x0001b098
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x0001b098
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+		>;
+	};
+
+	pinctrl_reset_gpio_led: reset-gpio-led-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18		0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+		>;
+	};
+
+	pinctrl_lcd_enable: lcdenablegrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x1b0b0 /* lcd enable */
+			MX6QDL_PAD_EIM_D16__GPIO3_IO16  0x1b0b0 /* sel6_8 */
+		>;
+	};
+
+	pinctrl_lm75: lm75grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
+		>;
+	};
+
+	pinctrl_proximity: proximitygrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11  0x1b0b0
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
+		>;
+	};
+
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
+		>;
+	};
+
+	pinctrl_pwm4: pwm4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
+		>;
+	};
+
+	pinctrl_rtc: rtc-grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
+		>;
+	};
+
+	pinctrl_ctouch: ctouch-grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
+			MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
+			MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
+			MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbh2_idle: usbh2-idle-grp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x00013018
+			MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
+		>;
+	};
+
+	pinctrl_usbh2_active: usbh2-active-grp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x00013018
+			MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
+		>;
+	};
+
+	pinctrl_usb3503: usb3503-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1    0x00000018
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12     0x1b0b0 /* USB INT */
+			MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
+			MX6QDL_PAD_SD1_DAT0__GPIO1_IO16    0x1b0b0 /* USB Connect */
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID	0x17059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x00017069
+			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x00010038
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
+			MX6QDL_PAD_GPIO_4__SD2_CD_B    0x0001b0b0
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x00017059
+			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x00010059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
+		>;
+	};
+
+	pinctrl_wdog1: wdoggrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+		>;
+	};
+};
--- a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi
@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+/*
+ * Special SoM hardware required which uses the pins from micro SD card. The
+ * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
+ * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
+ * card must be disabled and the uart1 rts/cts must be output on other DHCOM
+ * pins, see uart1 and usdhc3 node below.
+ */
+&can2 {
+	status = "okay";
+};
+
+&gpio1 {
+	/*
+	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+	 * GPIO line, however the i.MX6 UART driver assumes RX happens
+	 * during TX anyway and that it only controls drive enable DE
+	 * line. Hence, the RX is always enabled here.
+	 */
+	rs485-rx-en-hog {
+		gpio-hog;
+		gpios = <18 0>; /* GPIO Q */
+		line-name = "rs485-rx-en";
+		output-low;
+	};
+};
+
+&gpio3 {
+	gpio-line-names =
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "DRC02-In1", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
+		"DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
+		"", "", "", "", "DRC02-Out1", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
+		"", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&uart1 {
+	/*
+	 * Due to the use of can2 the signals for can2 Tx and Rx are routed to
+	 * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
+	 * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
+	 */
+	/delete-property/ uart-has-rtscts;
+	cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
+	pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
+	pinctrl-names = "default";
+	rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+};
+
+&uart5 {
+	/*
+	 * On DRC02 this UART is used as RS485 interface and RS485_TX_En is
+	 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
+	 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
+	 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
+	 * node above.
+	 */
+	/delete-property/ uart-has-rtscts;
+	linux,rs485-enabled-at-boot-time;
+	pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>;
+	pinctrl-names = "default";
+	rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
+};
+
+&usbh1 {
+	disable-over-current;
+};
+
+&usdhc2 { /* SD card */
+	status = "okay";
+};
+
+&usdhc3 {
+	/*
+	 * Due to the use of can2 the micro SD card on module have to be
+	 * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
+	 * can2 Tx and Rx.
+	 */
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * I: uart1 rts
+			 * M: uart1 cts
+			 * P: uart5 rs485-tx-en
+			 * Q: uart5 rs485-rx-en
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
+	pinctrl-names = "default";
+
+	pinctrl_uart5_core: uart5-core-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA	0x1b0b1
+			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA	0x1b0b1
+		>;
+	};
+};
--- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
@ -5,19 +5,6 @@

 #include "imx6qdl-dhcom-u-boot.dtsi"

-/ {
-	fec_vio: regulator-fec {
-		compatible = "regulator-fixed";
-
-		regulator-name = "fec-vio";
-		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
-	};
-};
-
 &fec {
 	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
-	phy-reset-duration = <1>;
-	phy-reset-post-delay = <10>;
-
-	phy-supply = <&fec_vio>;
 };
--- a/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi
@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_YELLOW>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+&gpio1 {
+	gpio-line-names =
+		"", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
+		"", "", "", "", "", "", "", "",
+		"DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+	gpio-line-names =
+		"", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
+		"DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "",
+		"", "", "", "", "PicoITX-Out1", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "",
+		"", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&iomuxc {
+	pinctrl-0 = <
+			/*
+			 * The following DHCOM GPIOs are used on this board.
+			 * Therefore, they have been removed from the list below.
+			 * I: yellow led
+			 */
+			&pinctrl_hog_base
+			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+			&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+			&pinctrl_dhcom_g &pinctrl_dhcom_h
+			&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+			&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
+			&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
+			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
+			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
+		>;
+	pinctrl-names = "default";
+};
--- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi
@ -1,8 +1,26 @@
 // SPDX-License-Identifier: (GPL-2.0+)
 /*
 * Copyright (C) 2020 Harald Seiler <hws@denx.de>
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
 */

+/ {
+	aliases {
+		eeprom0 = &eeprom0;
+	};
+};
+
+&fec {
+	phy-reset-duration = <1>;
+	phy-reset-post-delay = <10>;
+	phy-supply = <&reg_eth_vio>;
+};
+
+&i2c3 {
+	eeprom0: eeprom@50 {
+	};
+};
+
 &reg_usb_otg_vbus {
 	gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 	enable-active-high;
--- a/arch/arm/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi
@ -130,7 +130,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi
@ -196,7 +196,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi
@ -190,7 +190,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi
@ -227,7 +227,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw560x.dtsi
@ -281,7 +281,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5903.dtsi
@ -225,7 +225,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5904.dtsi
@ -203,7 +203,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";

 	fixed-link {
--- a/arch/arm/dts/imx6qdl-gw5907.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5907.dtsi
@ -132,7 +132,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5910.dtsi
@ -148,7 +148,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw5912.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5912.dtsi
@ -144,7 +144,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6qdl-gw5913.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5913.dtsi
@ -123,7 +123,7 @@
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <10>;
-	phy-reset-post-delay = <100>;
+	phy-reset-post-delay = <300>;
 	status = "okay";
 };

--- a/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi
+++ b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi
@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
+ */
+
+#include "imx6qdl-dhcom-u-boot.dtsi"
+
+&fec {
+	phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+};
--- a/arch/arm/dts/imx6s-dhcom-drc02.dts
+++ b/arch/arm/dts/imx6s-dhcom-drc02.dts
@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 DH electronics GmbH
+ *
+ * DHCOM iMX6 variant:
+ * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 493-400 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+/dts-v1/;
+
+/*
+ * The kernel only distinguishes between i.MX6 Quad and DualLite,
+ * but the Solo is actually a DualLite with only one CPU. So use
+ * DualLite for the Solo and disable one CPU node.
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-dhcom-som.dtsi"
+#include "imx6qdl-dhcom-drc02.dtsi"
+
+/ {
+	model = "DH electronics i.MX6S DHCOM on DRC02";
+	compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
+		     "fsl,imx6dl";
+
+	cpus {
+		/delete-node/ cpu@1;
+	};
+};
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
@ -392,7 +392,7 @@

 &i2c2 {
 	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
-	clock-frequency = <320000>;
+	clock-frequency = <100000>;
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@ -121,6 +121,10 @@
 	u-boot,dm-spl;
 };

+&pinctrl_wdog {
+	u-boot,dm-spl;
+};
+
 &fec1 {
 	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@ -80,6 +80,10 @@
 	u-boot,dm-spl;
 };

+&pinctrl_wdog {
+	u-boot,dm-spl;
+};
+
 &gpio1 {
 	u-boot,dm-spl;
 };
--- a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+	aliases {
+		eeprom0 = &eeprom0;
+		eeprom1 = &eeprom1;
+		mmc0 = &usdhc2;	/* MicroSD */
+		mmc1 = &usdhc3;	/* eMMC */
+		mmc2 = &usdhc1;	/* SDIO */
+	};
+
+	config {
+		dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+};
+
+&buck4 {
+	u-boot,dm-spl;
+};
+
+&buck5 {
+	u-boot,dm-spl;
+};
+
+&eqos {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&i2c3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c3_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+	u-boot,dm-spl;
+};
+
+&pmic {
+	u-boot,dm-spl;
+
+	regulators {
+		u-boot,dm-spl;
+	};
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&wdog1 {
+	u-boot,dm-spl;
+};
--- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts
@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/qca-ar803x.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mp-dhcom-som.dtsi"
+
+/ {
+	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
+	compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	gpio-keys {
+		#size-cells = <0>;
+		compatible = "gpio-keys";
+
+		button-0 {
+			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
+			label = "TA1-GPIO-A";
+			linux,code = <KEY_A>;
+			pinctrl-0 = <&pinctrl_dhcom_a>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-1 {
+			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
+			label = "TA2-GPIO-B";
+			linux,code = <KEY_B>;
+			pinctrl-0 = <&pinctrl_dhcom_b>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-2 {
+			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
+			label = "TA3-GPIO-C";
+			linux,code = <KEY_C>;
+			pinctrl-0 = <&pinctrl_dhcom_c>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+
+		button-3 {
+			gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
+			label = "TA4-GPIO-D";
+			linux,code = <KEY_D>;
+			pinctrl-0 = <&pinctrl_dhcom_d>;
+			pinctrl-names = "default";
+			wakeup-source;
+		};
+	};
+
+	led {
+		compatible = "gpio-leds";
+
+		led-5 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
+			pinctrl-0 = <&pinctrl_dhcom_e>;
+			pinctrl-names = "default";
+		};
+
+		led-6 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
+			pinctrl-0 = <&pinctrl_dhcom_f>;
+			pinctrl-names = "default";
+		};
+
+		led-7 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
+			pinctrl-0 = <&pinctrl_dhcom_h>;
+			pinctrl-names = "default";
+		};
+
+		led-8 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
+			pinctrl-0 = <&pinctrl_dhcom_i>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+/*
+ * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
+ * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
+ */
+/delete-node/ &ethphy0f;
+
+/*
+ * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
+ * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
+ */
+/delete-node/ &ethphy1f;
+
+&fec {	/* Second ethernet */
+	phy-handle = <&ethphypdk>;
+
+	mdio {
+		ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy1>;
+			pinctrl-names = "default";
+			reg = <7>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			rxc-skew-ps = <3000>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txc-skew-ps = <3000>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+			max-speed = <100>;
+		};
+	};
+};
+
+&flexcan1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	fsl,over-current-active-low;
+};
--- a/arch/arm/dts/imx8mp-dhcom-som.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@ -43,6 +43,10 @@
 	u-boot,dm-spl;
 };

+&pinctrl_wdog {
+	u-boot,dm-spl;
+};
+
 &gpio1 {
 	u-boot,dm-spl;
 };
--- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@ -9,6 +9,14 @@
 	};
 };

+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
+
 &binman {
 	 u-boot-spl-ddr {
 		filename = "u-boot-spl-ddr.bin";
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@ -2,30 +2,6 @@

 #include "imx8mq-u-boot.dtsi"

-&{/soc@0} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30000000} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30400000} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@32c00000} {
-	u-boot,dm-spl;
-};
-
-&iomuxc {
-	u-boot,dm-spl;
-};
-
 &pinctrl_uart1 {
 	u-boot,dm-spl;
 };
--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
@ -5,3 +5,11 @@
 &reg_usdhc2_vmmc {
 	u-boot,off-on-delay-us = <20000>;
 };
+
+&uart1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
--- a/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@ -10,6 +10,30 @@

 };

+&{/soc@0} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30000000} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30400000} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@32c00000} {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
 &binman {
 	u-boot-spl-ddr {
 		align = <4>;
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@ -723,6 +723,7 @@ void ddrphy_init_read_msg_block(enum fw_type type);

 void update_umctl2_rank_space_setting(unsigned int pstat_num);
 void get_trained_CDD(unsigned int fsp);
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);

 static inline void reg32_write(unsigned long addr, u32 val)
 {
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@ -48,6 +48,16 @@
 #ifdef CONFIG_IMX8MM
 #define USDHC3_BASE_ADDR	0x30B60000
 #endif
+#define UART_BASE_ADDR(n)	(			\
+	!!sizeof(struct {				\
+		static_assert((n) >= 1 && (n) <= 4);	\
+		int pad;				\
+		}) * (					\
+	(n) == 1 ? UART1_BASE_ADDR :			\
+	(n) == 2 ? UART2_BASE_ADDR :			\
+	(n) == 3 ? UART3_BASE_ADDR :			\
+	UART4_BASE_ADDR)				\
+	)

 #define TZASC_BASE_ADDR		0x32F80000

--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@ -17,6 +17,7 @@
 #define AHAB_WRITE_SECURE_FUSE_REQ_CID	0x91
 #define AHAB_FWD_LIFECYCLE_UP_REQ_CID   0x95
 #define AHAB_READ_FUSE_REQ_CID	0x97
+#define AHAB_GET_FW_VERSION_CID	0x9D
 #define AHAB_RELEASE_RDC_REQ_CID   0xC4
 #define AHAB_WRITE_FUSE_REQ_CID	0xD6
 #define AHAB_CAAM_RELEASE_CID 0xD7
@ -39,6 +40,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
 int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
 int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
 int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
 int ahab_dump_buffer(u32 *buffer, u32 buffer_length);

 #endif
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@ -179,16 +179,16 @@ struct fuse_bank0_regs {
 #define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
 #define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
 #define IMX_RTC_BASE		(0x07000 + IMX_IO_BASE)
-#define UART1_BASE		(0x0a000 + IMX_IO_BASE)
-#define UART2_BASE		(0x0b000 + IMX_IO_BASE)
-#define UART3_BASE		(0x0c000 + IMX_IO_BASE)
-#define UART4_BASE		(0x0d000 + IMX_IO_BASE)
+#define UART1_BASE_ADDR		(0x0a000 + IMX_IO_BASE)
+#define UART2_BASE_ADDR		(0x0b000 + IMX_IO_BASE)
+#define UART3_BASE_ADDR		(0x0c000 + IMX_IO_BASE)
+#define UART4_BASE_ADDR		(0x0d000 + IMX_IO_BASE)
 #define I2C1_BASE_ADDR		(0x12000 + IMX_IO_BASE)
 #define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
 #define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
 #define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
-#define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
-#define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
+#define UART5_BASE_ADDR		(0x1b000 + IMX_IO_BASE)
+#define UART6_BASE_ADDR		(0x1c000 + IMX_IO_BASE)
 #define I2C2_BASE_ADDR		(0x1D000 + IMX_IO_BASE)
 #define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
 #define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
@ -204,6 +204,18 @@ struct fuse_bank0_regs {

 #define NFC_BASE_ADDR		IMX_NFC_BASE

+#define UART_BASE_ADDR(n)	(			\
+	!!sizeof(struct {				\
+		static_assert((n) >= 1 && (n) <= 6);	\
+		int pad;				\
+		}) * (					\
+	(n) == 1 ? UART1_BASE_ADDR :			\
+	(n) == 2 ? UART2_BASE_ADDR :			\
+	(n) == 3 ? UART3_BASE_ADDR :			\
+	(n) == 4 ? UART4_BASE_ADDR :			\
+	(n) == 5 ? UART5_BASE_ADDR :			\
+	UART6_BASE_ADDR)				\
+	)

 /* FMCR System Control bit definition*/
 #define UART4_RXD_CTL	(1 << 25)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@ -598,6 +598,18 @@ struct esdc_regs {
 #define UART4_BASE	0x43FB0000
 #define UART5_BASE	0x43FB4000

+#define UART_BASE_ADDR(n)	(			\
+	!!sizeof(struct {				\
+		static_assert((n) >= 1 && (n) <= 5);	\
+		int pad;				\
+		}) * (					\
+	(n) == 1 ? UART1_BASE :				\
+	(n) == 2 ? UART2_BASE :				\
+	(n) == 3 ? UART3_BASE :				\
+	(n) == 4 ? UART4_BASE :				\
+	UART5_BASE_ADDR)				\
+	)
+
 #define I2C1_BASE_ADDR          0x43f80000
 #define I2C1_CLK_OFFSET		26
 #define I2C2_BASE_ADDR          0x43F98000
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@ -506,10 +506,6 @@ static int read_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb,
 	int ret = 0;

 	mtd = boot_cfg->mtd;
-	if (mtd_block_isbad(mtd, off)) {
-		printf("Block %d is bad, skipped\n", (int)CONV_TO_BLOCKS(off));
-		return 1;
-	}

 	fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
 	if (!fcb_raw_page) {
@ -530,7 +526,7 @@ static int read_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb,
 		else if (plat_config.misc_flags & FCB_ENCODE_BCH_40b)
 			mxs_nand_mode_fcb_40bit(mtd);

-		ret = nand_read(mtd, off, &size, (u_char *)fcb);
+		ret = nand_read_skip_bad(mtd, off, &size, NULL, mtd->size, (u_char *)fcb);

 		/* switch BCH back */
 		mxs_nand_mode_normal(mtd);
@ -617,6 +613,7 @@ static int write_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb)
 	for (i = 0; i < g_boot_search_count; i++) {
 		if (mtd_block_isbad(mtd, off)) {
 			printf("Block %d is bad, skipped\n", i);
+			off += mtd->erasesize;
 			continue;
 		}

@ -676,20 +673,15 @@ static int read_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt,
 		      void *dbbt_data_page, loff_t off)
 {
 	size_t size;
+	size_t actual_size;
 	struct mtd_info *mtd;
 	loff_t to;
 	int ret;

 	mtd = boot_cfg->mtd;

-	if (mtd_block_isbad(mtd, off)) {
-		printf("Block %d is bad, skipped\n",
-		       (int)CONV_TO_BLOCKS(off));
-		return 1;
-	}
-
 	size = sizeof(struct dbbt_block);
-	ret = nand_read(mtd, off, &size, (u_char *)dbbt);
+	ret = nand_read_skip_bad(mtd, off, &size, &actual_size, mtd->size, (u_char *)dbbt);
 	printf("NAND DBBT read from 0x%llx offset 0x%zx read: %s\n",
 	       off, size, ret ? "ERROR" : "OK");
 	if (ret)
@ -697,9 +689,9 @@ static int read_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt,

 	/* dbbtpages == 0 if no bad blocks */
 	if (dbbt->dbbtpages > 0) {
-		to = off + 4 * mtd->writesize;
+		to = off + 4 * mtd->writesize + actual_size - size;
 		size = mtd->writesize;
-		ret = nand_read(mtd, to, &size, dbbt_data_page);
+		ret = nand_read_skip_bad(mtd, to, &size, NULL, mtd->size, dbbt_data_page);
 		printf("DBBT data read from 0x%llx offset 0x%zx read: %s\n",
 		       to, size, ret ? "ERROR" : "OK");

@ -729,6 +721,7 @@ static int write_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt,
 		if (mtd_block_isbad(mtd, off)) {
 			printf("Block %d is bad, skipped\n",
 			       (int)(i + CONV_TO_BLOCKS(off)));
+			off += mtd->erasesize;
 			continue;
 		}

--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@ -100,7 +100,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@ -148,6 +148,13 @@ config TARGET_IMX8MN_VENICE
 	select GATEWORKS_SC
 	select MISC

+config TARGET_IMX8MP_DH_DHCOM_PDK2
+	bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
+	select BINMAN
+	select IMX8MP
+	select IMX8M_LPDDR4
+	select SUPPORT_SPL
+
 config TARGET_IMX8MP_EVK
 	bool "imx8mp LPDDR4 EVK board"
 	select BINMAN
@ -265,6 +272,7 @@ source "board/beacon/imx8mn/Kconfig"
 source "board/bsh/imx8mn_smm_s2/Kconfig"
 source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
 source "board/data_modul/imx8mm_edm_sbc/Kconfig"
+source "board/dhelectronics/dh_imx8mp/Kconfig"
 source "board/engicam/imx8mm/Kconfig"
 source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@ -72,15 +72,13 @@ void enable_tzc380(void)
 	 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
 	 * order to avoid AXI Bus errors when GPU is in use
 	 */
-	if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
-		setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);

 	/*
 	 * imx8mn and imx8mp implements the lock bit for
 	 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
 	 */
-	if (is_imx8mn() || is_imx8mp())
-		setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);

 	/*
 	 * set Region 0 attribute to allow secure and non-secure
@ -1410,7 +1408,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
@ -1535,6 +1533,16 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
 		return ENVL_UNKNOWN;

 	switch (dev) {
+	case USB_BOOT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+			return ENVL_MMC;
+		if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+			return ENVL_NOWHERE;
+		return ENVL_UNKNOWN;
 	case QSPI_BOOT:
 	case SPI_NOR_BOOT:
 		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
@ -1563,3 +1571,29 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
 }

 #endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+const struct rproc_att hostmap[] = {
+	/* aux core , host core,  size */
+	{ 0x00000000, 0x007e0000, 0x00020000 },
+	/* OCRAM_S */
+	{ 0x00180000, 0x00180000, 0x00008000 },
+	/* OCRAM */
+	{ 0x00900000, 0x00900000, 0x00020000 },
+	/* OCRAM */
+	{ 0x00920000, 0x00920000, 0x00020000 },
+	/* QSPI Code - alias */
+	{ 0x08000000, 0x08000000, 0x08000000 },
+	/* DDR (Code) - alias */
+	{ 0x10000000, 0x80000000, 0x0FFE0000 },
+	/* TCML */
+	{ 0x1FFE0000, 0x007E0000, 0x00040000 },
+	/* OCRAM_S */
+	{ 0x20180000, 0x00180000, 0x00008000 },
+	/* OCRAM */
+	{ 0x20200000, 0x00900000, 0x00040000 },
+	/* DDR (Data) */
+	{ 0x40000000, 0x40000000, 0x80000000 },
+	{ /* sentinel */ }
+};
+#endif
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@ -14,7 +14,13 @@
 #include <linux/compiler.h>
 #include <cpu_func.h>

-#ifndef CONFIG_IMX8M
+/* Just to avoid build error */
+#if CONFIG_IS_ENABLED(IMX8M)
+#define SRC_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_M4_ENABLE_MASK		BIT(0)
+#define SRC_M4_REG_OFFSET		0
+#endif
+
 const __weak struct rproc_att hostmap[] = { };

 static const struct rproc_att *get_host_mapping(unsigned long auxcore)
@ -36,10 +42,11 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore)
 * is valid, returns the entry point address.
 * Translates load addresses in the elf file to the U-Boot address space.
 */
-static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
+static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack)
 {
 	Elf32_Ehdr *ehdr; /* ELF header structure pointer */
 	Elf32_Phdr *phdr; /* Program header structure pointer */
+	int num = 0;
 	int i;

 	ehdr = (Elf32_Ehdr *)addr;
@ -54,19 +61,24 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
 			continue;

 		if (!mmap) {
-			printf("Invalid aux core address: %08x",
+			printf("Invalid aux core address: %08x\n",
 			       phdr->p_paddr);
 			return 0;
 		}

-		dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa;
+		dst = (void *)(ulong)(phdr->p_paddr - mmap->da) + mmap->sa;
 		src = (void *)addr + phdr->p_offset;

 		debug("Loading phdr %i to 0x%p (%i bytes)\n",
 		      i, dst, phdr->p_filesz);

-		if (phdr->p_filesz)
+		if (phdr->p_filesz) {
 			memcpy(dst, src, phdr->p_filesz);
+			/* Stack in __isr_vector is the first section/word */
+			if (!num)
+				*stack = *(uint32_t *)src;
+			num++;
+		}
 		if (phdr->p_filesz != phdr->p_memsz)
 			memset(dst + phdr->p_filesz, 0x00,
 			       phdr->p_memsz - phdr->p_filesz);
@ -77,7 +89,6 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr)

 	return ehdr->e_entry;
 }
-#endif

 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
@ -86,20 +97,17 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 	if (!addr)
 		return -EINVAL;

-#ifdef CONFIG_IMX8M
-	stack = *(u32 *)addr;
-	pc = *(u32 *)(addr + 4);
-#else
 	/*
 	 * handling ELF64 binaries
 	 * isn't supported yet.
 	 */
 	if (valid_elf_image(addr)) {
-		stack = 0x0;
-		pc = load_elf_image_m_core_phdr(addr);
+		pc = load_elf_image_m_core_phdr(addr, &stack);
 		if (!pc)
 			return CMD_RET_FAILURE;

+		if (!CONFIG_IS_ENABLED(ARM64))
+			stack = 0x0;
 	} else {
 		/*
 		 * Assume binary file with vector table at the beginning.
@ -109,7 +117,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 		stack = *(u32 *)addr;
 		pc = *(u32 *)(addr + 4);
 	}
-#endif
+
 	printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
 	       stack, pc);

@ -120,36 +128,32 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 	flush_dcache_all();

 	/* Enable M4 */
-#ifdef CONFIG_IMX8M
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
-		      0, 0, 0, 0, NULL);
-#else
-	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
-			SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
-#endif
+	if (CONFIG_IS_ENABLED(IMX8M)) {
+		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
+	} else {
+		clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+				SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+	}

 	return 0;
 }

 int arch_auxiliary_core_check_up(u32 core_id)
 {
-#ifdef CONFIG_IMX8M
 	struct arm_smccc_res res;
-
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
-		      0, 0, 0, 0, &res);
-
-	return res.a0;
-#else
 	unsigned int val;

+	if (CONFIG_IS_ENABLED(IMX8M)) {
+		arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
+		return res.a0;
+	}
+
 	val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);

 	if (val & SRC_M4C_NON_SCLR_RST_MASK)
 		return 0;  /* assert in reset */

 	return 1;
-#endif
 }

 /*
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@ -347,6 +347,20 @@ config TARGET_MX6Q_ENGICAM
 	select SUPPORT_SPL
 	imply CMD_DM

+config TARGET_MX6Q_ACC
+	bool "Support for Bosch ACC board"
+	depends on MX6QDL
+	select BOARD_LATE_INIT
+	select OF_CONTROL
+	select SPL_OF_LIBFDT
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_MX6SABREAUTO
 	bool "mx6sabreauto"
 	depends on MX6QDL
@ -686,6 +700,7 @@ source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
 source "board/freescale/mx6ullevk/Kconfig"
+source "board/bosch/acc/Kconfig"
 source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/phytec/pcl063/Kconfig"
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@ -744,7 +744,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
 	setup_serial_number();
 	return 0;
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@ -361,7 +361,7 @@ int arch_misc_init(void)
 		int ret;
 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@ -93,7 +93,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@ -950,7 +950,7 @@ int arch_misc_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}

 	return 0;
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@ -28,14 +28,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

-static const iomux_v3_cfg_t uart_pads[] = {
-	MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
 	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@ -81,8 +75,6 @@ int board_early_init_f(void)

 	set_wdog_reset(wdog);

-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
 	init_uart_clk(2);

 	return 0;
--- a/board/bosch/acc/Kconfig
+++ b/board/bosch/acc/Kconfig
@ -0,0 +1,19 @@
+if TARGET_MX6Q_ACC
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_BOARD
+	default "acc"
+
+config SYS_CONFIG_NAME
+	default "imx6q-bosch-acc"
+
+config SYS_BOOT_EMMC
+	bool "Boot from EMMC"
+	default y
+	help
+	  Say N here if you want to boot from SD card or microUSB.
+	  Say Y to boot from eMMC.
+
+endif
--- a/board/bosch/acc/MAINTAINERS
+++ b/board/bosch/acc/MAINTAINERS
@ -0,0 +1,9 @@
+MX6Q_ACC
+M:	Matthias Winker <matthias.winker@de.bosch.com>
+M:	Philip Oberfichtner <pro@denx.de>
+S:	Maintained
+F:	board/bosch/acc
+F:	include/configs/imx6q-bosch-acc.h
+F:	configs/imx6q_bosch_acc_defconfig
+F:	arch/arm/dts/imx6q-bosch-acc.dts
+F:	arch/arm/dts/imx6q-bosch-acc-u-boot.dts
--- a/board/bosch/acc/Makefile
+++ b/board/bosch/acc/Makefile
@ -0,0 +1,6 @@
+# Copyright (C) 2017
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := acc.o
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@ -0,0 +1,755 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
+ * Copyright (c) 2019 Bosch Thermotechnik GmbH
+ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/device-internal.h>
+#include <env.h>
+#include <env_internal.h>
+#include <hang.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <fuse.h>
+
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_ACC_PLAT_DETECT     IMX_GPIO_NR(5, 9)
+#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0)
+#define GPIO_BUZZER              IMX_GPIO_NR(1, 18)
+#define GPIO_LAN1_RESET          IMX_GPIO_NR(4, 27)
+#define GPIO_LAN2_RESET          IMX_GPIO_NR(4, 19)
+#define GPIO_LAN3_RESET          IMX_GPIO_NR(4, 18)
+#define GPIO_USB_HUB_RESET       IMX_GPIO_NR(5, 5)
+#define GPIO_EXP_RS485_RESET     IMX_GPIO_NR(4, 16)
+#define GPIO_TOUCH_RESET         IMX_GPIO_NR(1, 20)
+
+#define BOARD_INFO_MAGIC 0x19730517
+
+struct board_info {
+	int magic;
+	int board;
+	int rev;
+};
+
+static struct board_info *detect_board(void);
+
+#define PFID_BOARD_ACC 0xe
+
+static const char * const name_board[] = {
+	[PFID_BOARD_ACC] = "ACC",
+};
+
+#define PFID_REV_22 0x8
+#define PFID_REV_21 0x9
+#define PFID_REV_20 0xa
+#define PFID_REV_14 0xb
+#define PFID_REV_13 0xc
+#define PFID_REV_12 0xd
+#define PFID_REV_11 0xe
+#define PFID_REV_10 0xf
+
+static const char * const name_revision[] = {
+	[0 ... PFID_REV_10] = "Unknown",
+	[PFID_REV_10] = "1.0",
+	[PFID_REV_11] = "1.1",
+	[PFID_REV_12] = "1.2",
+	[PFID_REV_13] = "1.3",
+	[PFID_REV_14] = "1.4",
+	[PFID_REV_20] = "2.0",
+	[PFID_REV_21] = "2.1",
+	[PFID_REV_22] = "2.2",
+};
+
+/*
+ * NXP Reset Default: 0x0001B0B0
+ * - Schmitt trigger input (PAD_CTL_HYS)
+ * - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP)
+ * - Pull Enabled (PAD_CTL_PUE)
+ * - Pull/Keeper Enabled (PAD_CTL_PKE)
+ * - CMOS output (No PAD_CTL_ODE)
+ * - Medium Speed (PAD_CTL_SPEED_MED)
+ * - 40 Ohm drive strength (PAD_CTL_DSE_40ohm)
+ * - Slow (PAD_CTL_SRE_SLOW)
+ */
+
+/* Input, no pull up/down: 0x0x000100B0 */
+#define GPIN_PAD_CTRL (PAD_CTL_HYS \
+		| PAD_CTL_SPEED_MED \
+		| PAD_CTL_DSE_40ohm \
+		| PAD_CTL_SRE_SLOW)
+
+/* Input, pull up: 0x0x0001B0B0 */
+#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \
+		| PAD_CTL_PUS_100K_UP \
+		| PAD_CTL_PUE \
+		| PAD_CTL_PKE \
+		| PAD_CTL_SPEED_MED \
+		| PAD_CTL_DSE_40ohm \
+		| PAD_CTL_SRE_SLOW)
+
+/* Input, pull down: 0x0x000130B0 */
+#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \
+		| PAD_CTL_PUS_100K_DOWN \
+		| PAD_CTL_PUE \
+		| PAD_CTL_PKE \
+		| PAD_CTL_SPEED_MED \
+		| PAD_CTL_DSE_40ohm \
+		| PAD_CTL_SRE_SLOW)
+
+static const iomux_v3_cfg_t board_detect_pads[] = {
+	/* Platform detect */
+	IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	/* RAM Volt detect */
+	IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	/* PFID 0..9 */
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	/* Manufacturer */
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
+	/* Redundant */
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL))
+};
+
+static int gpio_acc_pfid[] = {
+	IMX_GPIO_NR(2, 0),
+	IMX_GPIO_NR(2, 1),
+	IMX_GPIO_NR(2, 2),
+	IMX_GPIO_NR(2, 3),
+	IMX_GPIO_NR(2, 4),
+	IMX_GPIO_NR(6, 14),
+	IMX_GPIO_NR(6, 15),
+	IMX_GPIO_NR(2, 5),
+	IMX_GPIO_NR(2, 6),
+	IMX_GPIO_NR(2, 7),
+	IMX_GPIO_NR(6, 16),
+	IMX_GPIO_NR(5, 4),
+};
+
+static int init_gpio(int nr)
+{
+	int ret;
+
+	ret = gpio_request(nr, "");
+	if (ret != 0) {
+		printf("Could not request gpio nr: %d\n", nr);
+		hang();
+	}
+	ret = gpio_direction_input(nr);
+	if (ret != 0) {
+		printf("Could not set gpio nr: %d to input\n", nr);
+		hang();
+	}
+	return 0;
+}
+
+/*
+ * We want to detect the board type only once in SPL,
+ * so we store the board_info struct at beginning in IRAM.
+ *
+ * U-Boot itself can read it also, and do not need again
+ * to detect board type.
+ *
+ */
+static struct board_info *detect_board(void)
+{
+	struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR;
+	int i;
+
+	if (binfo->magic == BOARD_INFO_MAGIC)
+		return binfo;
+
+	puts("Board: ");
+	SETUP_IOMUX_PADS(board_detect_pads);
+	init_gpio(GPIO_ACC_PLAT_DETECT);
+	if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) {
+		puts("not supported");
+		hang();
+	} else {
+		puts("Bosch ");
+	}
+
+	for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++)
+		init_gpio(gpio_acc_pfid[i]);
+
+	binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 |
+	    gpio_get_value(gpio_acc_pfid[1]) << 1 |
+	    gpio_get_value(gpio_acc_pfid[2]) << 2 |
+	    gpio_get_value(gpio_acc_pfid[11]) << 3;
+	printf("%s ", name_board[binfo->board]);
+
+	binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 |
+	    gpio_get_value(gpio_acc_pfid[8]) << 1 |
+	    gpio_get_value(gpio_acc_pfid[9]) << 2 |
+	    gpio_get_value(gpio_acc_pfid[10]) << 3;
+	printf("rev: %s\n", name_revision[binfo->rev]);
+
+	binfo->magic = BOARD_INFO_MAGIC;
+
+	return binfo;
+}
+
+static void unset_early_gpio(void)
+{
+	init_gpio(GPIO_LAN1_RESET);
+	init_gpio(GPIO_LAN2_RESET);
+	init_gpio(GPIO_LAN3_RESET);
+	init_gpio(GPIO_USB_HUB_RESET);
+	init_gpio(GPIO_EXP_RS485_RESET);
+	init_gpio(GPIO_TOUCH_RESET);
+
+	gpio_set_value(GPIO_LAN1_RESET, 1);
+	gpio_set_value(GPIO_LAN2_RESET, 1);
+	gpio_set_value(GPIO_LAN3_RESET, 1);
+	gpio_set_value(GPIO_USB_HUB_RESET, 1);
+	gpio_set_value(GPIO_EXP_RS485_RESET, 1);
+	gpio_set_value(GPIO_TOUCH_RESET, 1);
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_MMC;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_MMC;
+	}
+
+	return ENVL_UNKNOWN;
+}
+
+int board_late_init(void)
+{
+	struct board_info *binfo = detect_board();
+
+	switch (binfo->board) {
+	case PFID_BOARD_ACC:
+		env_set("bootconf", "conf-imx6q-bosch-acc.dtb");
+		break;
+	default:
+		printf("Unknown board %d\n", binfo->board);
+		break;
+	}
+
+	unset_early_gpio();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+/* Early
+ * - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an
+ *   external pull-down resistor)
+ * - Touch clean reset on every boot
+ * - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init
+ */
+static const iomux_v3_cfg_t early_pads[] = {
+	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */
+	IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */
+	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */
+	IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */
+	IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */
+	IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */
+	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */
+};
+
+static void setup_iomux_early(void)
+{
+	SETUP_IOMUX_PADS(early_pads);
+}
+
+static void set_early_gpio(void)
+{
+	init_gpio(GPIO_BUZZER);
+	init_gpio(GPIO_LAN1_RESET);
+	init_gpio(GPIO_LAN2_RESET);
+	init_gpio(GPIO_LAN3_RESET);
+	init_gpio(GPIO_USB_HUB_RESET);
+	init_gpio(GPIO_EXP_RS485_RESET);
+	init_gpio(GPIO_TOUCH_RESET);
+
+	/* Reset signals are active low */
+	gpio_set_value(GPIO_BUZZER, 0);
+	gpio_set_value(GPIO_LAN1_RESET, 0);
+	gpio_set_value(GPIO_LAN2_RESET, 0);
+	gpio_set_value(GPIO_LAN3_RESET, 0);
+	gpio_set_value(GPIO_USB_HUB_RESET, 0);
+	gpio_set_value(GPIO_EXP_RS485_RESET, 0);
+	gpio_set_value(GPIO_TOUCH_RESET, 0);
+}
+
+/* UART */
+#define UART_PAD_CTRL \
+		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+		PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#undef UART_PAD_CTRL
+#define UART_PAD_CTRL 0x1b0b1
+static const iomux_v3_cfg_t uart2_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart2_pads);
+}
+
+void spl_board_init(void)
+{
+}
+
+static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00008038,
+	.dram_sdclk_1 = 0x00008038,
+	.dram_cas = 0x00008028,
+	.dram_ras = 0x00008028,
+	.dram_reset = 0x00000028,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00008000,
+	.dram_sdodt0 = 0x00000028,
+	.dram_sdodt1 = 0x00000028,
+	.dram_sdqs0 = 0x00008038,
+	.dram_sdqs1 = 0x00008038,
+	.dram_sdqs2 = 0x00008038,
+	.dram_sdqs3 = 0x00008038,
+	.dram_sdqs4 = 0x00008038,
+	.dram_sdqs5 = 0x00008038,
+	.dram_sdqs6 = 0x00008038,
+	.dram_sdqs7 = 0x00008038,
+	.dram_dqm0 = 0x00008038,
+	.dram_dqm1 = 0x00008038,
+	.dram_dqm2 = 0x00008038,
+	.dram_dqm3 = 0x00008038,
+	.dram_dqm4 = 0x00008038,
+	.dram_dqm5 = 0x00008038,
+	.dram_dqm6 = 0x00008038,
+	.dram_dqm7 = 0x00008038,
+};
+
+static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = {
+	.grp_ddr_type = 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000028,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000038,
+	.grp_b1ds = 0x00000038,
+	.grp_b2ds = 0x00000038,
+	.grp_b3ds = 0x00000038,
+	.grp_b4ds = 0x00000038,
+	.grp_b5ds = 0x00000038,
+	.grp_b6ds = 0x00000038,
+	.grp_b7ds = 0x00000038,
+};
+
+static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0020001F,
+	.p0_mpwldectrl1 = 0x00280021,
+	.p1_mpwldectrl0 = 0x00120028,
+	.p1_mpwldectrl1 = 0x000D001F,
+	.p0_mpdgctrl0 = 0x43340342,
+	.p0_mpdgctrl1 = 0x03300325,
+	.p1_mpdgctrl0 = 0x4334033E,
+	.p1_mpdgctrl1 = 0x03280270,
+	.p0_mprddlctl = 0x46373B3E,
+	.p1_mprddlctl = 0x3B383544,
+	.p0_mpwrdlctl = 0x36383E40,
+	.p1_mpwrdlctl = 0x4030433A,
+};
+
+/* Micron MT41K128M16JT-125 (standard - 1600,CL=11)
+ * !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!!
+ * So this setting is actually invalid!
+ *
+static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+ */
+
+/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E)
+ * Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss
+ * width set to 64, as four chips are used on acc (4 * 16 = 64)
+ */
+static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 64,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1313, // 13.125ns
+	.trcmin = 5063, // 50.625ns
+	.trasmin = 3750, // 37.5ns
+	.SRT = 0, // Set to 1 for temperatures above 85°C
+};
+
+static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = {
+	.ddr_type = DDR_TYPE_DDR3,
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize = 2,
+	.cs_density = 32,	/* 32Gb per CS */
+	.ncs = 1,		/* single chip select */
+	.cs1_mirror = 0,
+	.rtt_wr = 1,		/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom = 1,		/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat = 0,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x33,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x33,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+#define ACC_SPREAD_SPECTRUM_STOP	0x0fa
+#define ACC_SPREAD_SPECTRUM_STEP	0x001
+#define ACC_SPREAD_SPECTRUM_DENOM	0x190
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Turn clocks on/off */
+	writel(0x00C0000F, &ccm->CCGR0);
+	writel(0x0030FC00, &ccm->CCGR1);
+	writel(0x03FF0033, &ccm->CCGR2);
+	writel(0x3FF3300F, &ccm->CCGR3);
+	writel(0x0003C300, &ccm->CCGR4);
+	writel(0x0F3000C3, &ccm->CCGR5);
+	writel(0x00000FFF, &ccm->CCGR6);
+
+	/* Enable spread spectrum */
+	writel(BM_ANADIG_PLL_528_SS_ENABLE |
+	       BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) |
+	       BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP),
+	       &ccm->analog_pll_528_ss);
+
+	writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM),
+	       &ccm->analog_pll_528_denom);
+}
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+
+static const iomux_v3_cfg_t usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)),
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)),
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)),	/* CD */
+};
+
+static const iomux_v3_cfg_t usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 1, 4},
+	{USDHC4_BASE_ADDR, 1, 8},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	detect_board();
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		return !gpio_get_value(USDHC2_CD_GPIO);
+	case USDHC4_BASE_ADDR:
+		return 1;	/* eMMC always present */
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	gpio_direction_input(USDHC2_CD_GPIO);
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node) (Physical Port)
+	 * mmc0 USDHC2
+	 * mmc1 USDHC4
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc4_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 bmode = imx6_src_get_boot_mode();
+	u8 boot_dev = BOOT_DEVICE_MMC1;
+
+	detect_board();
+
+	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		/* SD/eSD - BOOT_DEVICE_MMC1 */
+		if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) {
+			/*
+			 * boot from SD is not allowed, if boot from eMMC is
+			 * configured.
+			 */
+			puts("SD boot not allowed\n");
+			spl_boot_list[0] = BOOT_DEVICE_NONE;
+			return;
+		}
+
+		boot_dev = BOOT_DEVICE_MMC1;
+		break;
+
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/* MMC/eMMC */
+		boot_dev = BOOT_DEVICE_MMC2;
+		break;
+	default:
+		/* Default - BOOT_DEVICE_MMC1 */
+		printf("Wrong board boot order\n");
+		break;
+	}
+
+	spl_boot_list[0] = boot_dev;
+}
+
+static void setup_ddr(void)
+{
+	struct board_info *binfo = detect_board();
+
+	switch (binfo->rev) {
+	case PFID_REV_20:
+	case PFID_REV_21:
+	case PFID_REV_22:
+	default:
+		/* Rev 2 board has i.MX6 Dual with 64-bit RAM */
+		mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width,
+				 &acc_mx6d_ddr_ioregs,
+				 &acc_mx6d_grp_ioregs);
+		mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib,
+			     &acc_mx6d_mem_ddr3_1066);
+		/* Perform DDR DRAM calibration */
+		udelay(100);
+		mmdc_do_write_level_calibration(&acc_mx6d_ddr_info);
+		mmdc_do_dqs_calibration(&acc_mx6d_ddr_info);
+		break;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog power-down counter (only enabled after reset) */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* Enable device tree and early DM support*/
+	spl_early_init();
+
+	/* Setup early required pinmuxes */
+	setup_iomux_early();
+	set_early_gpio();
+
+	/* Setup UART pinmux */
+	setup_iomux_uart();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	setup_ddr();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
+
+#if IS_ENABLED(CONFIG_USB_EHCI_MX6)
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		BIT(9)
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				  port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "imx6q-bosch-acc"))
+		return 0;
+	return -1;
+}
+
+void reset_cpu(ulong addr)
+{
+	puts("Hanging CPU for watchdog reset!\n");
+	hang();
+}
+
+#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
+void show_boot_progress(int val)
+{
+	u32 fuseval;
+	int ret;
+
+	if (val < 0)
+		val *= -1;
+
+	switch (val) {
+	case BOOTSTAGE_ID_ENTER_CLI_LOOP:
+		printf("autoboot failed, check fuse\n");
+		ret = fuse_read(0, 6, &fuseval);
+		if (ret == 0 && (fuseval & 0x2) == 0x0) {
+			printf("Enter cmdline, as device not closed\n");
+			return;
+		}
+		ret = fuse_read(5, 7, &fuseval);
+		if (ret == 0 && fuseval == 0x0) {
+			printf("Enter cmdline, as it is a Development device\n");
+			return;
+		}
+		panic("do not enter cmdline");
+		break;
+	}
+}
+#endif
--- a/board/bsh/imx8mn_smm_s2/spl.c
+++ b/board/bsh/imx8mn_smm_s2/spl.c
@ -40,19 +40,8 @@ void spl_board_init(void)
 		puts("Failed to find clock node. Check device tree\n");
 }

-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static const iomux_v3_cfg_t wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-	set_wdog_reset(wdog);
-
 	init_uart_clk(3);

 	if (IS_ENABLED(CONFIG_NAND_MXS)) {
@ -83,6 +72,8 @@ void board_init_f(ulong dummy)

 	preloader_console_init();

+	enable_tzc380();
+
 	/* DDR initialization */
 	spl_dram_init();

--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@ -24,33 +24,6 @@

 #include <linux/delay.h>

-static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
-{
-	unsigned int tmp;
-
-	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
-	do {
-		tmp = reg32_read(DDRC_MRSTAT(0));
-	} while (tmp & 0x1);
-
-	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
-	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
-	reg32setbit(DDRC_MRCTRL0(0), 31);
-	do {
-		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
-	} while ((tmp & 0x8) == 0);
-	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
-	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
-	while (tmp) { //try to find a significant byte in the word
-		if (tmp & 0xff) {
-			tmp &= 0xff;
-			break;
-		}
-		tmp >>= 8;
-	}
-	return tmp;
-}
-
 struct lpddr4_desc {
 	char name[16];
 	unsigned int id;
--- a/board/data_modul/imx8mm_edm_sbc/spl.c
+++ b/board/data_modul/imx8mm_edm_sbc/spl.c
@ -28,14 +28,8 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

-static const iomux_v3_cfg_t uart_pads[] = {
-	IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
 	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@ -47,8 +41,6 @@ static void data_modul_imx8mm_edm_sbc_early_init_f(void)
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));

 	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }

 static int data_modul_imx8mm_edm_sbc_board_power_init(void)
@ -149,8 +141,6 @@ void board_init_f(ulong dummy)

 	data_modul_imx8mm_edm_sbc_early_init_f();

-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);

@ -160,6 +150,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}

+	preloader_console_init();
+
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@ -100,9 +100,9 @@ static int setup_dhcom_mac_from_fuse(void)
 		return 0;
 	}

-	eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
+	eeprom = ofnode_get_aliases_node("eeprom0");
 	if (!ofnode_valid(eeprom)) {
-		printf("Invalid hardware path to EEPROM!\n");
+		printf("Can't find eeprom0 alias!\n");
 		return -ENODEV;
 	}

@ -225,16 +225,35 @@ int checkboard(void)
 }

 #ifdef CONFIG_MULTI_DTB_FIT
+static int strcmp_prefix(const char *s1, const char *s2)
+{
+	size_t n;
+
+	n = min(strlen(s1), strlen(s2));
+	return strncmp(s1, s2, n);
+}
+
 int board_fit_config_name_match(const char *name)
 {
-	if (is_mx6dq()) {
-		if (!strcmp(name, "imx6q-dhcom-pdk2"))
-			return 0;
-	} else if (is_mx6sdl()) {
-		if (!strcmp(name, "imx6dl-dhcom-pdk2"))
+	char *want;
+	char *have;
+
+	/* Test Board suffix, e.g. -dhcom-drc02 */
+	want = strchr(CONFIG_DEFAULT_DEVICE_TREE, '-');
+	have = strchr(name, '-');
+
+	if (!want || !have || strcmp(want, have))
+		return -EINVAL;
+
+	/* Test SoC prefix */
+	if (is_mx6dq() && !strcmp_prefix(name, "imx6q-"))
+		return 0;
+
+	if (is_mx6sdl()) {
+		if (!strcmp_prefix(name, "imx6s-") || !strcmp_prefix(name, "imx6dl-"))
 			return 0;
 	}

-	return -1;
+	return -EINVAL;
 }
 #endif
--- a/board/dhelectronics/dh_imx8mp/Kconfig
+++ b/board/dhelectronics/dh_imx8mp/Kconfig
@ -0,0 +1,15 @@
+if TARGET_IMX8MP_DH_DHCOM_PDK2
+
+config SYS_BOARD
+	default "dh_imx8mp"
+
+config SYS_VENDOR
+	default "dhelectronics"
+
+config SYS_CONFIG_NAME
+	default "imx8mp_dhcom_pdk2"
+
+config IMX_CONFIG
+	default "board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg"
+
+endif
--- a/board/dhelectronics/dh_imx8mp/MAINTAINERS
+++ b/board/dhelectronics/dh_imx8mp/MAINTAINERS
@ -0,0 +1,8 @@
+DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	arch/arm/dts/imx8mp-dhcom-pdk2.dts
+F:	arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
+F:	board/dhelectronics/imx8mp_dhcom_pdk2/
+F:	configs/imx8mp_dhcom_pdk2_defconfig
+F:	include/configs/imx8mp_dhcom_pdk2.h
--- a/board/dhelectronics/dh_imx8mp/Makefile
+++ b/board/dhelectronics/dh_imx8mp/Makefile
@ -0,0 +1,13 @@
+#
+# Copyright (C) 2022 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o lpddr4_timing_4G_32.o
+else
+obj-y += imx8mp_dhcom_pdk2.o
+endif
+
+obj-y += common.o
--- a/board/dhelectronics/dh_imx8mp/common.c
+++ b/board/dhelectronics/dh_imx8mp/common.c
@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u8 dh_get_memcfg(void)
+{
+	struct gpio_desc gpio[4];
+	u8 memcfg = 0;
+	ofnode node;
+	int i, ret;
+
+	node = ofnode_path("/config");
+	if (!ofnode_valid(node)) {
+		printf("%s: no /config node?\n", __func__);
+		return BIT(2) | BIT(0);
+	}
+
+	ret = gpio_request_list_by_name_nodev(node,
+					      "dh,ram-coding-gpios",
+					      gpio, ARRAY_SIZE(gpio),
+					      GPIOD_IS_IN);
+	for (i = 0; i < ret; i++)
+		memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
+
+	gpio_free_list_nodev(gpio, ret);
+
+	return memcfg;
+}
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <env.h>
+#include <env_internal.h>
+#include <i2c_eeprom.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+	u8 memcfg = dh_get_memcfg();
+
+	*size = (u64)memsz[memcfg] << 20ULL;
+
+	return 0;
+}
+
+/* IMX8M SNVS registers needed for the bootcount functionality */
+#define SNVS_BASE_ADDR			0x30370000
+#define SNVS_LPSR			0x4c
+#define SNVS_LPLVDR			0x64
+#define SNVS_LPPGDR_INIT		0x41736166
+
+static void setup_snvs(void)
+{
+	/* Enable SNVS clock */
+	clock_enable(CCGR_SNVS, 1);
+	/* Initialize glitch detect */
+	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+	/* Clear interrupt status */
+	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
+static void setup_eqos(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Set INTF as RGMII, enable RGMII TXC clock. */
+	clrsetbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
+	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
+
+	set_clk_eqos(ENET_125MHZ);
+}
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Enable RGMII TX clk output. */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+
+	set_clk_enet(ENET_125MHZ);
+}
+
+static int setup_mac_address_from_eeprom(char *alias, char *env, bool odd)
+{
+	unsigned char enetaddr[6];
+	struct udevice *dev;
+	int ret, offset;
+
+	offset = fdt_path_offset(gd->fdt_blob, alias);
+	if (offset < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return offset;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, offset, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM!\n");
+		return ret;
+	}
+
+	ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+	if (ret) {
+		printf("Error reading configuration EEPROM!\n");
+		return ret;
+	}
+
+	/*
+	 * Populate second ethernet MAC from first ethernet EEPROM with MAC
+	 * address LSByte incremented by 1. This is only used on SoMs without
+	 * second ethernet EEPROM, i.e. early prototypes.
+	 */
+	if (odd)
+		enetaddr[5]++;
+
+	eth_env_set_enetaddr(env, enetaddr);
+
+	return 0;
+}
+
+static void setup_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	bool skip_eth0 = false;
+	bool skip_eth1 = false;
+	int ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		skip_eth0 = true;
+
+	ret = eth_env_get_enetaddr("eth1addr", enetaddr);
+	if (ret)	/* eth1addr is already set */
+		skip_eth1 = true;
+
+	/* Both MAC addresses are already set in U-Boot environment. */
+	if (skip_eth0 && skip_eth1)
+		return;
+
+	/*
+	 * If IIM fuses contain valid MAC address, use it.
+	 * The IIM MAC address fuses are NOT programmed by default.
+	 */
+	imx_get_mac_from_fuse(0, enetaddr);
+	if (is_valid_ethaddr(enetaddr)) {
+		if (!skip_eth0)
+			eth_env_set_enetaddr("ethaddr", enetaddr);
+		/*
+		 * The LSbit of MAC address in fuses is always 0, use the
+		 * next consecutive MAC address for the second ethernet.
+		 */
+		enetaddr[5]++;
+		if (!skip_eth1)
+			eth_env_set_enetaddr("eth1addr", enetaddr);
+		return;
+	}
+
+	/* Use on-SoM EEPROMs with pre-programmed MAC address. */
+	if (!skip_eth0) {
+		/* We cannot do much more if this returns -ve . */
+		setup_mac_address_from_eeprom("eeprom0", "ethaddr", false);
+	}
+
+	if (!skip_eth1) {
+		ret = setup_mac_address_from_eeprom("eeprom1", "eth1addr",
+						    false);
+		if (ret) {	/* Second EEPROM might not be populated. */
+			/* We cannot do much more if this returns -ve . */
+			setup_mac_address_from_eeprom("eeprom0", "eth1addr",
+						      true);
+		}
+	}
+}
+
+int board_init(void)
+{
+	setup_eqos();
+	setup_fec();
+	setup_snvs();
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_mac_address();
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
+}
--- a/board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg
+++ b/board/dhelectronics/dh_imx8mp/imximage-lpddr4.cfg
@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x920000
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+
+u8 dh_get_memcfg(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/pca9450.h>
+
+#include "lpddr4_timing.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static const iomux_v3_cfg_t uart_pads[] = {
+	MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX8MP_PAD_SAI2_RXC__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t wdog_pads[] = {
+	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static void dh_imx8mp_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static int dh_imx8mp_board_power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("Failed to get PMIC\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output. */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/* Increase VDD_SOC to typical value 0.95V before first DRAM access. */
+	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV))
+		/* Set DVS0 to 0.85V for special case. */
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+	else
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c);
+
+	/* Set DVS1 to 0.85v for suspend. */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+
+	/*
+	 * Enable DVS control through PMIC_STBY_REQ and
+	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H).
+	 */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Kernel uses OD/OD frequency for SoC. */
+
+	/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+
+	/* Set WDOG_B_CFG to cold reset. */
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+	/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
+	pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
+
+	return 0;
+}
+
+static struct dram_timing_info *dram_timing_info[8] = {
+	NULL,					/* 512 MiB */
+	NULL,					/* 1024 MiB */
+	NULL,					/* 1536 MiB */
+	NULL,					/* 2048 MiB */
+	NULL,					/* 3072 MiB */
+	&dh_imx8mp_dhcom_dram_timing_32g_x32,	/* 4096 MiB */
+	NULL,					/* 6144 MiB */
+	NULL,					/* 8192 MiB */
+};
+
+static void spl_dram_init(void)
+{
+	const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+	u8 memcfg = dh_get_memcfg();
+	int i;
+
+	printf("DDR:   %d MiB [0x%x]\n", size[memcfg], memcfg);
+
+	if (!dram_timing_info[memcfg]) {
+		printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
+		       memcfg);
+		for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
+			if (dram_timing_info[i])	/* Configuration found */
+				break;
+	}
+
+	ddr_init(dram_timing_info[memcfg]);
+}
+
+void spl_board_init(void)
+{
+	/*
+	 * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
+	 * allow to change it. Should set the clock after PMIC setting done.
+	 * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
+	 * ND VDD_SOC.
+	 */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+	clock_enable(CCGR_GIC, 1);
+}
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	dh_imx8mp_early_init_f();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+
+	enable_tzc380();
+
+	dh_imx8mp_board_power_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@ -57,7 +57,7 @@ void spl_board_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
 	puts("Normal Boot\n");
 }
@ -72,23 +72,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif

-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	return 0;
-}
-
 static int power_init_board(void)
 {
 	struct udevice *dev;
@ -135,8 +118,6 @@ void board_init_f(ulong dummy)

 	init_uart_clk(1);

-	board_early_init_f();
-
 	timer_init();

 	/* Clear the BSS. */
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@ -52,7 +52,7 @@ void spl_board_init(void)
 	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
 	puts("Normal Boot\n");

@ -115,23 +115,6 @@ int board_fit_config_name_match(const char *name)
 }
 #endif

-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	return 0;
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
@ -140,8 +123,6 @@ void board_init_f(ulong dummy)

 	init_uart_clk(1);

-	board_early_init_f();
-
 	timer_init();

 	/* Clear the BSS. */
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@ -20,23 +20,6 @@

 DECLARE_GLOBAL_DATA_PTR;

-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	return 0;
-}
-
 static void setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@ -43,7 +43,7 @@ void spl_board_init(void)

 		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 		if (ret)
-			printf("Failed to initialize %s: %d\n", dev->name, ret);
+			printf("Failed to initialize caam_jr: %d\n", ret);
 	}
 	/*
 	 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
@ -134,8 +134,6 @@ void board_init_f(ulong dummy)

 	init_uart_clk(1);

-	board_early_init_f();
-
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@ -58,6 +58,23 @@ int power_init_board(void)
 	return 0;
 }

+void display_ele_fw_version(void)
+{
+	u32 fw_version, sha1, res;
+	int ret;
+
+	ret = ahab_get_fw_version(&fw_version, &sha1, &res);
+	if (ret) {
+		printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
+	} else {
+		printf("ELE firmware version %u.%u.%u-%x",
+		       (fw_version & (0x00ff0000)) >> 16,
+		       (fw_version & (0x0000ff00)) >> 8,
+		       (fw_version & (0x000000ff)), sha1);
+		((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
+	}
+}
+
 void spl_board_init(void)
 {
 	struct udevice *dev;
@ -77,6 +94,8 @@ void spl_board_init(void)

 	puts("Normal Boot\n");

+	display_ele_fw_version();
+
 	/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */

 	/* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@ -1,471 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Gateworks Corporation
- *
- * Author: Tim Harvey <tharvey@gateworks.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <common.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/global_data.h>
-#include <dm/device.h>
-#include <dm/uclass.h>
-
-#include "ventana_eeprom.h"
-#include "gsc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
-struct udevice *i2c_get_dev(int busno, int slave)
-{
-	struct udevice *dev, *bus;
-	int ret;
-
-	ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
-	if (ret)
-		return NULL;
-	ret = dm_i2c_probe(bus, slave, 0, &dev);
-	if (ret)
-		return NULL;
-
-	return dev;
-}
-#endif
-
-/*
- * The Gateworks System Controller will fail to ACK a master transaction if
- * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
- * When this does occur, it will never be busy long enough to fail more than
- * 2 back-to-back transfers.  Thus we wrap i2c_read and i2c_write with
- * 3 retries.
- */
-int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
-	int retry = 3;
-	int n = 0;
-	int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
-	if (!dev)
-		return -ENODEV;
-	ret = i2c_set_chip_offset_len(dev, alen);
-	if (ret) {
-		puts("EEPROM: Failed to set alen\n");
-		return ret;
-	}
-#else
-	i2c_set_bus_num(CONFIG_I2C_GSC);
-#endif
-
-	while (n++ < retry) {
-#if CONFIG_IS_ENABLED(DM_I2C)
-		ret = dm_i2c_read(dev, addr, buf, len);
-#else
-		ret = i2c_read(chip, addr, alen, buf, len);
-#endif
-		if (!ret)
-			break;
-		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
-		      n, ret);
-		if (ret != -EREMOTEIO)
-			break;
-		mdelay(10);
-	}
-	return ret;
-}
-
-int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
-{
-	int retry = 3;
-	int n = 0;
-	int ret;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	dev = i2c_get_dev(CONFIG_I2C_GSC, chip);
-	if (!dev)
-		return -ENODEV;
-	ret = i2c_set_chip_offset_len(dev, alen);
-	if (ret) {
-		puts("EEPROM: Failed to set alen\n");
-		return ret;
-	}
-#endif
-
-	while (n++ < retry) {
-#if CONFIG_IS_ENABLED(DM_I2C)
-		ret = dm_i2c_write(dev, addr, buf, len);
-#else
-		ret = i2c_write(chip, addr, alen, buf, len);
-#endif
-		if (!ret)
-			break;
-		debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
-		      n, ret);
-		if (ret != -EREMOTEIO)
-			break;
-		mdelay(10);
-	}
-	mdelay(100);
-	return ret;
-}
-
-int gsc_get_board_temp(void)
-{
-	const void *fdt = gd->fdt_blob;
-	int node, reg, mode, val;
-	const char *label;
-	u8 buf[2];
-	int ret;
-
-	node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
-	if (node <= 0)
-		return node;
-
-	/* iterate over hwmon nodes */
-	node = fdt_first_subnode(fdt, node);
-	while (node > 0) {
-		reg = fdtdec_get_int(fdt, node, "reg", -1);
-		mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
-		label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
-
-		if ((reg == -1) || (mode == -1) || !label) {
-			printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
-			continue;
-		}
-
-		if ((mode != 0) || strcmp(label, "temp"))
-			continue;
-
-		memset(buf, 0, sizeof(buf));
-		ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
-		val = buf[0] | buf[1] << 8;
-		if (val >= 0) {
-			if (val > 0x8000)
-				val -= 0xffff;
-			return val;
-		}
-		node = fdt_next_subnode(fdt, node);
-	}
-
-	return 0;
-}
-
-/* display hardware monitor ADC channels */
-int gsc_hwmon(void)
-{
-	const void *fdt = gd->fdt_blob;
-	int node, reg, mode, len, val, offset;
-	const char *label;
-	u8 buf[2];
-	int ret;
-
-	node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
-	if (node <= 0)
-		return node;
-
-	/* iterate over hwmon nodes */
-	node = fdt_first_subnode(fdt, node);
-	while (node > 0) {
-		reg = fdtdec_get_int(fdt, node, "reg", -1);
-		mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
-		offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
-		label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
-
-		if ((reg == -1) || (mode == -1) || !label)
-			printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
-
-		memset(buf, 0, sizeof(buf));
-		ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf));
-		val = buf[0] | buf[1] << 8;
-		if (val >= 0) {
-			const u32 *div;
-			int r[2];
-
-			switch (mode) {
-			case 0: /* temperature (C*10) */
-				if (val > 0x8000)
-					val -= 0xffff;
-				printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
-				break;
-			case 1: /* prescaled voltage */
-				if (val != 0xffff)
-					printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
-				break;
-			case 2: /* scaled based on ref volt and resolution */
-				val *= 2500;
-				val /= 1 << 12;
-
-				/* apply pre-scaler voltage divider */
-				div  = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
-				if (div && (len == sizeof(uint32_t) * 2)) {
-					r[0] = fdt32_to_cpu(div[0]);
-					r[1] = fdt32_to_cpu(div[1]);
-					if (r[0] && r[1]) {
-						val *= (r[0] + r[1]);
-						val /= r[1];
-					}
-				}
-
-				/* adjust by offset */
-				val += (offset / 1000);
-
-				printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
-				break;
-			}
-		}
-		node = fdt_next_subnode(fdt, node);
-	}
-
-	return 0;
-}
-
-int gsc_info(int verbose)
-{
-	unsigned char buf[16];
-
-	if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
-		return CMD_RET_FAILURE;
-
-	printf("GSC:   v%d", buf[GSC_SC_FWVER]);
-	printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
-	printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
-		? "en" : "dis");
-	if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
-		buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
-		puts(" WDT_RESET");
-		gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
-			      &buf[GSC_SC_STATUS], 1);
-	}
-	printf(" board temp at %dC", gsc_get_board_temp() / 10);
-	puts("\n");
-	if (!verbose)
-		return CMD_RET_SUCCESS;
-
-	gsc_hwmon();
-
-	return 0;
-}
-
-/*
- *  The Gateworks System Controller implements a boot
- *  watchdog (always enabled) as a workaround for IMX6 boot related
- *  errata such as:
- *    ERR005768 - no fix scheduled
- *    ERR006282 - fixed in silicon r1.2
- *    ERR007117 - fixed in silicon r1.3
- *    ERR007220 - fixed in silicon r1.3
- *    ERR007926 - no fix scheduled
- *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
- *
- * Disable the boot watchdog
- */
-int gsc_boot_wd_disable(void)
-{
-	u8 reg;
-
-	if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
-		reg |= (1 << GSC_SC_CTRL1_WDDIS);
-		if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-			return 0;
-	}
-	puts("Error: could not disable GSC Watchdog\n");
-	return 1;
-}
-
-/* determine BOM revision from model */
-int get_bom_rev(const char *str)
-{
-	int  rev_bom = 0;
-	int i;
-
-	for (i = strlen(str) - 1; i > 0; i--) {
-		if (str[i] == '-')
-			break;
-		if (str[i] >= '1' && str[i] <= '9') {
-			rev_bom = str[i] - '0';
-			break;
-		}
-	}
-	return rev_bom;
-}
-
-/* determine PCB revision from model */
-char get_pcb_rev(const char *str)
-{
-	char rev_pcb = 'A';
-	int i;
-
-	for (i = strlen(str) - 1; i > 0; i--) {
-		if (str[i] == '-')
-			break;
-		if (str[i] >= 'A') {
-			rev_pcb = str[i];
-			break;
-		}
-	}
-	return rev_pcb;
-}
-
-/*
- * get dt name based on model and detail level:
- */
-const char *gsc_get_dtb_name(int level, char *buf, int sz)
-{
-	const char *model = (const char *)ventana_info.model;
-	const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-";
-	int modelno, rev_pcb, rev_bom;
-
-	/* a few board models are dt equivalents to other models */
-	if (strncasecmp(model, "gw5906", 6) == 0)
-		model = "gw552x-d";
-	else if (strncasecmp(model, "gw5908", 6) == 0)
-		model = "gw53xx-f";
-	else if (strncasecmp(model, "gw5905", 6) == 0)
-		model = "gw5904-a";
-
-	modelno = ((model[2] - '0') * 1000)
-		  + ((model[3] - '0') * 100)
-		  + ((model[4] - '0') * 10)
-		  + (model[5] - '0');
-	rev_pcb = tolower(get_pcb_rev(model));
-	rev_bom = get_bom_rev(model);
-
-	/* compare model/rev/bom in order of most specific to least */
-	snprintf(buf, sz, "%s%04d", pre, modelno);
-	switch (level) {
-	case 0: /* full model first (ie gw5400-a1) */
-		if (rev_bom) {
-			snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom);
-			break;
-		}
-		fallthrough;
-	case 1: /* don't care about bom rev (ie gw5400-a) */
-		snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb);
-		break;
-	case 2: /* don't care about the pcb rev (ie gw5400) */
-		snprintf(buf, sz, "%sgw%04d", pre, modelno);
-		break;
-	case 3: /* look for generic model (ie gw540x) */
-		snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10);
-		break;
-	case 4: /* look for more generic model (ie gw54xx) */
-		snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100);
-		break;
-	default: /* give up */
-		return NULL;
-	}
-
-	return buf;
-}
-
-#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
-static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc,
-			char *const argv[])
-{
-	unsigned char reg;
-	unsigned long secs = 0;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
-	secs = dectoul(argv[1], NULL);
-	printf("GSC Sleeping for %ld seconds\n", secs);
-
-	reg = (secs >> 24) & 0xff;
-	if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, &reg, 1))
-		goto error;
-	reg = (secs >> 16) & 0xff;
-	if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, &reg, 1))
-		goto error;
-	reg = (secs >> 8) & 0xff;
-	if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, &reg, 1))
-		goto error;
-	reg = secs & 0xff;
-	if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, &reg, 1))
-		goto error;
-	if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-		goto error;
-	reg |= (1 << 2);
-	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-		goto error;
-	reg &= ~(1 << 2);
-	reg |= 0x3;
-	if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-		goto error;
-
-	return CMD_RET_SUCCESS;
-
-error:
-	printf("i2c error\n");
-	return CMD_RET_FAILURE;
-}
-
-static int do_gsc_wd(struct cmd_tbl *cmdtp, int flag, int argc,
-		     char *const argv[])
-{
-	unsigned char reg;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
-	if (strcasecmp(argv[1], "enable") == 0) {
-		int timeout = 0;
-
-		if (argc > 2)
-			timeout = dectoul(argv[2], NULL);
-		if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-			return CMD_RET_FAILURE;
-		reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
-		if (timeout == 60)
-			reg |= (1 << GSC_SC_CTRL1_WDTIME);
-		else
-			timeout = 30;
-		reg |= (1 << GSC_SC_CTRL1_WDEN);
-		if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-			return CMD_RET_FAILURE;
-		printf("GSC Watchdog enabled with timeout=%d seconds\n",
-		       timeout);
-	} else if (strcasecmp(argv[1], "disable") == 0) {
-		if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-			return CMD_RET_FAILURE;
-		reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
-		if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
-			return CMD_RET_FAILURE;
-		printf("GSC Watchdog disabled\n");
-	} else {
-		return CMD_RET_USAGE;
-	}
-	return CMD_RET_SUCCESS;
-}
-
-static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
-	if (argc < 2)
-		return gsc_info(1);
-
-	if (strcasecmp(argv[1], "wd") == 0)
-		return do_gsc_wd(cmdtp, flag, --argc, ++argv);
-	else if (strcasecmp(argv[1], "sleep") == 0)
-		return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
-
-	return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(
-	gsc, 4, 1, do_gsc, "GSC configuration",
-	"[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
-	);
-
-#endif /* CONFIG_CMD_GSC */
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@ -32,9 +32,10 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_phy_config(struct phy_device *phydev)
 {
 	unsigned short val;
+	ofnode node;

-	/* Marvel 88E1510 */
-	if (phydev->phy_id == 0x1410dd1) {
+	switch (phydev->phy_id) {
+	case 0x1410dd1:
 		puts("MV88E1510");
 		/*
 		 * Page 3, Register 16: LED[2:0] Function Control Register
@ -47,10 +48,8 @@ int board_phy_config(struct phy_device *phydev)
 		val |= 0x0017;
 		phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
-	}
-
-	/* TI DP83867 */
-	else if (phydev->phy_id == 0x2000a231) {
+		break;
+	case 0x2000a231:
 		puts("TIDP83867 ");
 		/* LED configuration */
 		val = 0;
@ -66,6 +65,22 @@ int board_phy_config(struct phy_device *phydev)
 		val &= ~0x1f00;
 		val |= 0x0b00; /* chD tx clock*/
 		phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+		break;
+	case 0xd565a401:
+		puts("GPY111 ");
+		node = phy_get_ofnode(phydev);
+		if (ofnode_valid(node)) {
+			u32 rx_delay, tx_delay;
+
+			rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
+			tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
+			val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
+			val &= ~((0x7 << 12) | (0x7 << 8));
+			val |= (rx_delay / 500) << 12;
+			val |= (tx_delay / 500) << 8;
+			phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
+		}
+		break;
 	}

 	if (phydev->drv->config)
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@ -87,37 +87,20 @@ static void spl_dram_init(int size)
 	ddr_init(dram_timing);
 }

-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

 #ifdef CONFIG_IMX8MM
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const wdog_pads[] = {
 	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
 #elif CONFIG_IMX8MN
-static const iomux_v3_cfg_t uart_pads[] = {
-	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
 	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
 #elif CONFIG_IMX8MP
-static const iomux_v3_cfg_t uart_pads[] = {
-	MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
 	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
-
 #endif

 int board_early_init_f(void)
@ -128,8 +111,6 @@ int board_early_init_f(void)

 	set_wdog_reset(wdog);

-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
 	return 0;
 }

@ -276,8 +257,6 @@ void board_init_f(ulong dummy)

 	timer_init();

-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);

@ -287,6 +266,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}

+	preloader_console_init();
+
 	enable_tzc380();

 	/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@ -226,16 +226,21 @@ static const char *lvds_compat_string;

 static int detect_lvds(struct display_info_t const *dev)
 {
+	struct udevice *idev, *ibus;
 	u8 touchid[23];
 	u8 *touchptr = &touchid[0];
 	int ret;

-	ret = i2c_set_bus_num(0);
+	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
+	if (ret)
+		return 0;
+
+	ret = dm_i2c_probe(ibus, 0x38, 0, &idev);
 	if (ret)
 		return 0;

 	/* Touchscreen is at address 0x38, ID register is 0xbb. */
-	ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
+	ret = dm_i2c_read(idev, 0xbb, touchid, sizeof(touchid));
 	if (ret)
 		return 0;

@ -385,23 +390,6 @@ splasherr:
 	return 0;
 }

-#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c_pads[] = {
-		/* I2C1 */
-		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
-		/* I2C2 */
-		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
 static void setup_iomux_video(void)
 {
 	static const iomux_v3_cfg_t lcd_pads[] = {
@ -505,7 +493,6 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 	setup_iomux_fec();
-	setup_iomux_i2c();
 	setup_iomux_nand();
 	setup_iomux_video();

--- a/board/menlo/mx8menlo/mx8menlo.c
+++ b/board/menlo/mx8menlo/mx8menlo.c
@ -12,19 +12,6 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <spl.h>

-#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-/* Verdin UART_3, Console/Debug UART */
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_SAI3_TXFS_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_SAI3_TXC_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 #define SNVS_BASE_ADDR		0x30370000
 #define SNVS_LPSR		0x4c
 #define SNVS_LPLVDR		0x64
@ -42,14 +29,6 @@ static void setup_snvs(void)

 void board_early_init(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
 	init_uart_clk(1);

 	setup_snvs();
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@ -74,30 +74,10 @@ int board_fit_config_name_match(const char *name)
 }
 #endif

-#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-/* Verdin UART_3, Console/Debug UART */
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};

 __weak void board_early_init(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
 	init_uart_clk(0);
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }

 int power_init_board(void)
@ -143,8 +123,6 @@ void board_init_f(ulong dummy)

 	timer_init();

-	preloader_console_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);

@ -162,6 +140,8 @@ void board_init_f(ulong dummy)
 		hang();
 	}

+	preloader_console_init();
+
 	enable_tzc380();

 	power_init_board();
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@ -24,7 +24,6 @@
 DECLARE_GLOBAL_DATA_PTR;

 #define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

 /* Verdin UART_3, Console/Debug UART */
 static const iomux_v3_cfg_t uart_pads[] = {
@ -32,18 +31,8 @@ static const iomux_v3_cfg_t uart_pads[] = {
 	MX8MP_PAD_UART3_TXD__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };

-static const iomux_v3_cfg_t wdog_pads[] = {
-	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));

 	init_uart_clk(2);
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@ -43,15 +43,12 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
 			       ulong size, void *dst)
 {
 	int err;
-#ifdef CONFIG_SYS_NAND_BLOCK_SIZE
 	ulong sector;

 	sector = *(int *)load->priv;
-	offs = sector + nand_spl_adjust_offset(sector, offs - sector);
-#else
 	offs *= load->bl_len;
 	size *= load->bl_len;
-#endif
+	offs = sector + nand_spl_adjust_offset(sector, offs - sector);
 	err = nand_spl_load_image(offs, size, dst);
 	if (err)
 		return 0;
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SYS_MALLOC_LEN=0x2400000
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@ -53,7 +53,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
+CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17780000
+CONFIG_SYS_MALLOC_LEN=0x01000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x1fe000
+CONFIG_MX6QDL=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_MX6Q_ACC=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-bosch-acc"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=8
+CONFIG_SPL_SIZE_LIMIT=69632
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x1ff000
+CONFIG_IMX_HAB=y
+# CONFIG_CMD_BMODE is not set
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_BUILD_TARGET=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_RAW_IMAGE_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xaa
+# CONFIG_SPL_CRC32 is not set
+# CONFIG_SPL_CRYPTO is not set
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_FUSE is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_PINMUX is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_SLEEP is not set
+# CONFIG_CMD_MP is not set
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_EXT4=y
+CONFIG_DOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_ENV_APPEND=y
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_DM_BOOTCOUNT=y
+CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
+CONFIG_IMX_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FS_FAT=y
+CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
+# CONFIG_EFI_LOADER is not set
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SPL_GPIO=y
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_LEN=0x2000000
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@ -105,6 +105,7 @@ CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@ -200,7 +200,6 @@ CONFIG_DM_RTC=y
 CONFIG_RTC_M41T62=y
 CONFIG_CONS_INDEX=2
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@ -41,6 +41,8 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
@ -82,4 +84,14 @@ CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_IMX_WATCHDOG=y
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@ -0,0 +1,244 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xFE0000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk2"
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_BOOTCOUNT_BOOTLIMIT=3
+CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0xFF0000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=16384
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_BKOPS_ENABLE=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_HASH_VERIFY=y
+CONFIG_CMD_BTRFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
+CONFIG_MMC_SPEED_MODE_SET=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE_AUTO=y
+CONFIG_ENV_SPI_MAX_HZ=80000000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_TSIZE=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_SPL_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_M41T62=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_USB_FUNCTION_ACM=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@ -27,7 +27,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_LEN=0x2000000
@ -135,6 +133,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_LEN=0x2000000
@ -136,6 +134,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@ -112,7 +112,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
-# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@ -78,6 +78,7 @@ CONFIG_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@ -83,5 +83,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_DM_THERMAL=y
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@ -37,7 +37,7 @@ CONFIG_SPL_WATCHDOG=y
 CONFIG_SPL_ATF=y
 CONFIG_CMD_NVEDIT_EFI=y
 # CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_UNZIP=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
--- a/Show More
+++ b/Show More