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u-boot/configs/chromebook_jerry_defconfig

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rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_CHROMEBOOK_JERRY=y
rockchip: spl: Support full-speed CPU in SPL Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:45:17 +00:00
CONFIG_ROCKCHIP_FAST_SPL=y
common: add CMD_GPIO to Kconfig Add CMD_GPIO to Kconfig and run tools/moveconfig.py . Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-11 13:39:33 +00:00
CONFIG_SPL_STACK_R_ADDR=0x80000
rockchip: jerry: Enable the Chrome OS EC Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:44:13 +00:00
CONFIG_DM_KEYBOARD=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
CONFIG_SPL_STACK_R=y
rockchip: Correct the defconfig order This has got out of sequence somehow. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:35 +00:00
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
rockchip: Use a separate clock ID for clocks At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:38 +00:00
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_REGMAP=y
dm: core: Add SPL Kconfig for REGMAP and SYSCON Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-17 06:20:13 +00:00
CONFIG_SPL_REGMAP=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_SYSCON=y
rockchip: Correct the defconfig order This has got out of sequence somehow. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:35 +00:00
CONFIG_SPL_SYSCON=y
rockchip: Disable simple-bus in SPL for firefly-rk3288, jerry This is not needed for booting, so drop it from SPL to save about 300 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:49 +00:00
# CONFIG_SPL_SIMPLE_BUS is not set
Reorder defconfigs with 'savedefconfig' Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-28 12:14:15 +00:00
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
rockchip: jerry: Enable the Chrome OS EC Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:44:13 +00:00
CONFIG_I2C_CROS_EC_TUNNEL=y
Reorder defconfigs with 'savedefconfig' Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-28 12:14:15 +00:00
CONFIG_SYS_I2C_ROCKCHIP=y
rockchip: jerry: Enable the Chrome OS EC Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:44:13 +00:00
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
rockchip: Use pwrseq for MMC start-up on jerry This is defined in the device tree in Linux. Copy over the settings so that this can be used instead of hard-coding the reset line. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:36 +00:00
CONFIG_PWRSEQ=y
Reorder defconfigs with 'savedefconfig' Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-28 12:14:15 +00:00
CONFIG_RESET=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
rockchip: Fix the configuration for chromebook_jerry Various updates did not make it through to this board. Also the instructions for building a SPI image are no-longer correct. Fix these so that Jerry can boot to a prompt again. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-29 12:22:45 +00:00
# CONFIG_SPL_PINCTRL_FULL is not set
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_ROCKCHIP_PINCTRL=y
CONFIG_DM_PMIC=y
rockchip: jerry: Enable the Chrome OS EC Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:44:13 +00:00
# CONFIG_SPL_PMIC_CHILDREN is not set
rockchip: jerry: Enable the RK808 PMIC and regulator Enable this PMIC and regulator, which is used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:48 +00:00
CONFIG_PMIC_RK808=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_DM_REGULATOR=y
rockchip: jerry: Enable the RK808 PMIC and regulator Enable this PMIC and regulator, which is used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:48 +00:00
CONFIG_REGULATOR_RK808=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_RAM=y
CONFIG_SPL_RAM=y
Reorder defconfigs with 'savedefconfig' Some boards' defconfigs are disordered. Reorder them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-09-28 12:14:15 +00:00
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
ns16550: move CONFIG_SYS_NS16550 to Kconfig Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-19 13:48:14 +00:00
CONFIG_SYS_NS16550=y
rockchip: Correct the defconfig order This has got out of sequence somehow. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-22 02:43:35 +00:00
CONFIG_ROCKCHIP_SPI=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_USE_PRIVATE_LIBGCC=y
rockchip: Fix the configuration for chromebook_jerry Various updates did not make it through to this board. Also the instructions for building a SPI image are no-longer correct. Fix these so that Jerry can boot to a prompt again. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-29 12:22:45 +00:00
CONFIG_USE_TINY_PRINTF=y
rockchip: Add basic support for jerry This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:42 +00:00
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
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