u-boot/drivers/cache/Makefile


obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
dm: cache: Create a uclass for cache The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:03 +00:00
spl: Allow cache drivers to be used in SPL Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 2019-10-11 05:48:33 +00:00			`obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o`
dm: cache: Create a uclass for cache The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:03 +00:00			`obj-$(CONFIG_SANDBOX) += sandbox_cache.o`
dm: cache: add the pl310 cache controller driver Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 2019-04-23 21:55:04 +00:00			`obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o`
cache: Add Arteris Ncore cache coherent unit driver Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 2019-11-27 07:55:24 +00:00			`obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o`
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2019-08-28 10:46:06 +00:00			`obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o`