leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
b340199f82
u-boot/include/fsl_errata.h

92 lines
2.0 KiB
C
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
/*
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
* Copyright 2013 - 2015 Freescale Semiconductor, Inc.
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
*/
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
#ifndef _FSL_ERRATA_H
#define _FSL_ERRATA_H
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
#include <common.h>
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
#if defined(CONFIG_PPC)
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
#include <asm/processor.h>
armv7: ls1021a: Drop macro CONFIG_LS102XA Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-27 18:41:03 +00:00
#elif defined(CONFIG_ARCH_LS1021A)
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
#include <asm/arch-ls102xa/immap_ls102xa.h>
#elif defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/soc.h>
#endif
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
static inline bool has_erratum_a006379(void)
{
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
powerpc/85xx: update erratum a006379 Enable Erratum A006379 for T2080, T2081, T4160, B4420. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-06 05:23:21 +00:00
((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-04-25 08:31:22 +00:00
((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
powerpc/85xx: update erratum a006379 Enable Erratum A006379 for T2080, T2081, T4160, B4420. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-06 05:23:21 +00:00
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-09-16 19:49:31 +00:00
return true;
return false;
}
#endif
powerpc/mpc85xx: modify erratum A007186 T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function has_errata_a007186 to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the sil has errata a007186, then run the errata code, if not, doesn't run the code. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-30 06:07:39 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
static inline bool has_erratum_a007186(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
case SVR_T4240:
return IS_SVR_REV(svr, 2, 0);
case SVR_T4160:
return IS_SVR_REV(svr, 2, 0);
case SVR_B4860:
return IS_SVR_REV(svr, 2, 0);
case SVR_B4420:
return IS_SVR_REV(svr, 2, 0);
case SVR_T2081:
case SVR_T2080:
powerpc/t2080: enable erratum_a007186 for t2080 rev1.1 T2080 rev1.1 also needs erratum a007186. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-09 09:12:22 +00:00
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
powerpc/mpc85xx: modify erratum A007186 T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function has_errata_a007186 to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the sil has errata a007186, then run the errata code, if not, doesn't run the code. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-10-30 06:07:39 +00:00
}
return false;
}
#endif
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
fsl/ddr: updated ddr errata-A008378 for arm and power SoCs DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:04 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
static inline bool has_erratum_a008378(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
armv7: ls1021a: Drop macro CONFIG_LS102XA Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-27 18:41:03 +00:00
#ifdef CONFIG_ARCH_LS1021A
fsl/ddr: updated ddr errata-A008378 for arm and power SoCs DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:04 +00:00
case SOC_VER_LS1020:
case SOC_VER_LS1021:
case SOC_VER_LS1022:
case SOC_VER_SLS1020:
return IS_SVR_REV(svr, 1, 0);
#endif
#ifdef CONFIG_PPC
case SVR_T1023:
case SVR_T1024:
return IS_SVR_REV(svr, 1, 0);
case SVR_T1020:
case SVR_T1022:
case SVR_T1040:
case SVR_T1042:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
default:
return false;
}
}
#endif
fsl/errata: move fsl_errata.h to common directory move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-20 07:52:03 +00:00
#endif /* _FSL_ERRATA_H */
Reference in New Issue Copy Permalink