2012-12-11 13:34:16 +00:00
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/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra30";
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2012-12-21 22:59:15 +00:00
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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2013-01-11 23:07:04 +00:00
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apbdma: dma {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04>;
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};
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2012-12-21 22:59:15 +00:00
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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/* PERIPH_ID_I2C1, CLK_M */
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clocks = <&tegra_car 12>;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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/* PERIPH_ID_I2C2, CLK_M */
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clocks = <&tegra_car 54>;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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/* PERIPH_ID_I2C3, CLK_M */
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clocks = <&tegra_car 67>;
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};
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i2c@7000c700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C700 0x100>;
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/* PERIPH_ID_I2C4, CLK_M */
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clocks = <&tegra_car 103>;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000D000 0x100>;
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/* PERIPH_ID_I2C_DVC, CLK_M */
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clocks = <&tegra_car 47>;
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};
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2012-12-11 13:34:16 +00:00
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};
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