443 lines
9.4 KiB
C
443 lines
9.4 KiB
C
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/*
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* (C) Copyright 2002
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* Daniel Engstr<EFBFBD>m, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Based on sc520cdp.c from rolo 1.6:
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*----------------------------------------------------------------------
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions GmbH
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* Klein-Winternheim, Germany
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*----------------------------------------------------------------------
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/ali512x.h>
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/* ALI M5123 Logical device numbers:
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* 0 FDC
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* 1 unused?
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* 2 unused?
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* 3 lpt
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* 4 UART1
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* 5 UART2
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* 6 RTC
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* 7 mouse/kbd
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* 8 CIO
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*/
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/*
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************************************************************
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* Some access primitives for the ALi chip: *
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************************************************************
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*/
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static void ali_write(u8 index, u8 value)
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{
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/* write an arbirary register */
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outb(index, ALI_INDEX);
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outb(value, ALI_DATA);
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}
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static int ali_read(u8 index)
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{
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outb(index, ALI_INDEX);
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return inb(ALI_DATA);
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}
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#define ALI_OPEN() \
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outb(0x51, ALI_DATA); \
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outb(0x23, ALI_DATA)
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#define ALI_CLOSE() \
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outb(0xbb, ALI_DATA)
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/* Select a logical device */
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#define ALI_SELDEV(dev) \
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ali_write(0x07, dev)
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void ali512x_init(void)
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{
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ALI_OPEN();
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ali_write(0x02, 0x01); /* soft reset */
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ali_write(0x03, 0x03); /* disable access to CIOs */
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ali_write(0x22, 0x00); /* disable direct powerdown */
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ali_write(0x23, 0x00); /* disable auto powerdown */
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ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
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ALI_CLOSE();
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}
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void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
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{
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ALI_OPEN();
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ALI_SELDEV(0);
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ali_write(0x30, enabled?1:0);
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if (enabled) {
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ali_write(0x60, io >> 8);
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ali_write(0x61, io & 0xff);
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ali_write(0x70, irq);
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ali_write(0x74, dma_channel);
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/* AT mode, no drive swap */
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ali_write(0xf0, 0x08);
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ali_write(0xf1, 0x00);
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ali_write(0xf2, 0xff);
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ali_write(0xf4, 0x00);
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}
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ALI_CLOSE();
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}
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void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
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{
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ALI_OPEN();
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ALI_SELDEV(3);
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ali_write(0x30, enabled?1:0);
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if (enabled) {
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ali_write(0x60, io >> 8);
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ali_write(0x61, io & 0xff);
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ali_write(0x70, irq);
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ali_write(0x74, dma_channel);
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/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
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ali_write(0xf0, 0xbc);
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/* 12 MHz, Burst DMA in ECP */
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ali_write(0xf1, 0x05);
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}
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ALI_CLOSE();
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}
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void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
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{
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ALI_OPEN();
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ALI_SELDEV(index?5:4);
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ali_write(0x30, enabled?1:0);
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if (enabled) {
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ali_write(0x60, io >> 8);
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ali_write(0x61, io & 0xff);
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ali_write(0x70, irq);
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ali_write(0xf0, 0x00);
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ali_write(0xf1, 0x00);
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/* huh? write 0xf2 twice - a typo in rolo
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* or some secret ali errata? Who knows?
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*/
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if (index) {
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ali_write(0xf2, 0x00);
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}
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ali_write(0xf2, 0x0c);
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}
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ALI_CLOSE();
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}
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void ali512x_set_uart2_irda(int enabled)
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{
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ALI_OPEN();
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ALI_SELDEV(5);
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ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
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ALI_CLOSE();
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}
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void ali512x_set_rtc(int enabled, u16 io, u8 irq)
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{
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ALI_OPEN();
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ALI_SELDEV(6);
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ali_write(0x30, enabled?1:0);
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if (enabled) {
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ali_write(0x60, io >> 8);
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ali_write(0x61, io & 0xff);
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ali_write(0x70, irq);
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ali_write(0xf0, 0x00);
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}
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ALI_CLOSE();
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}
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void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
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{
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ALI_OPEN();
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ALI_SELDEV(7);
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ali_write(0x30, enabled?1:0);
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if (enabled) {
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ali_write(0x70, kbc_irq);
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ali_write(0x72, mouse_irq);
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ali_write(0xf0, 0x00);
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}
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ALI_CLOSE();
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}
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/* Common I/O
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*
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* (This descripotsion is base on several incompete sources
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* since I have not been able to obtain any datasheet for the device
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* there may be some mis-understandings burried in here.
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* -- Daniel daniel@omicron.se)
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*
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* There are 22 CIO pins numbered
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* 10-17
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* 20-25
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* 30-37
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*
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* 20-24 are dedicated CIO pins, the other 17 are muliplexed with
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* other functions.
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*
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* Secondary
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* CIO Pin Function Decription
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* =======================================================
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* CIO10 IRQIN1 Interrupt input 1?
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* CIO11 IRQIN2 Interrupt input 2?
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* CIO12 IRRX IrDa Receive
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* CIO13 IRTX IrDa Transmit
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* CIO14 P21 KBC P21 fucntion
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* CIO15 P20 KBC P21 fucntion
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* CIO16 I2C_CLK I2C Clock
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* CIO17 I2C_DAT I2C Data
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*
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* CIO20 -
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* CIO21 -
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* CIO22 -
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* CIO23 -
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* CIO24 -
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* CIO25 LOCK Keylock
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*
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* CIO30 KBC_CLK Keybaord Clock
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* CIO31 CS0J General Chip Select decoder CS0J
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* CIO32 CS1J General Chip Select decoder CS1J
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* CIO33 ALT_KCLK Alternative Keyboard Clock
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* CIO34 ALT_KDAT Alternative Keyboard Data
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* CIO35 ALT_MCLK Alternative Mouse Clock
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* CIO36 ALT_MDAT Alternative Mouse Data
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* CIO37 ALT_KBC Alternative KBC select
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*
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* The CIO use a double indirect address scheme.
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*
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* Reigster 3 in the SIO is used to selectg where the CIO
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* I/O registers show up under function 8. Note that these
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* registers clash with the CIO function select regsters,
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* below.
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*
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* SIO reigster 3 (CIO Address Selection) bit definitions:
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* bit 7 CIO data register enabled
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* bit 1-0 CIO indirect registers select
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* 0 index = 0xE0 data = 0xE1
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* 1 index = 0xE2 data = 0xE3
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* 2 index = 0xE4 data = 0xE5
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* 3 index = 0xEA data = 0xEB
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*
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* There are three CIO I/O register accessed via CIO index and CIO data
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* 0x01 CIO 10-17 data
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* 0x02 CIO 20-25 data (bits 7-6 unused)
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* 0x03 CIO 30-37 data
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*
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*
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* The pin function is accessed through normal
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* SIO registers, each register have the same format:
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*
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* Bit Function Value
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* 0 Input/output 1=input
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* 1 Polarity of signal 1=inverted
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* 2 Unused ??
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* 3 Function (normal or special) 1=special
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* 7-4 Unused
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*
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* SIO REG
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* 0xe0 CIO 10 Config
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* 0xe1 CIO 11 Config
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* 0xe2 CIO 12 Config
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* 0xe3 CIO 13 Config
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* 0xe4 CIO 14 Config
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* 0xe5 CIO 15 Config
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* 0xe6 CIO 16 Config
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* 0xe7 CIO 16 Config
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*
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* 0xe8 CIO 20 Config
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* 0xe9 CIO 21 Config
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* 0xea CIO 22 Config
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* 0xeb CIO 23 Config
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* 0xec CIO 24 Config
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* 0xed CIO 25 Config
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*
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* 0xf5 CIO 30 Config
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* 0xf6 CIO 31 Config
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* 0xf7 CIO 32 Config
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* 0xf8 CIO 33 Config
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* 0xf9 CIO 34 Config
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* 0xfa CIO 35 Config
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* 0xfb CIO 36 Config
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* 0xfc CIO 37 Config
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*
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*/
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void ali512x_set_cio(int enabled)
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{
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int i;
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ALI_OPEN();
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ali_write(0x3, 3); /* Disable CIO data register */
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ALI_SELDEV(8);
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ali_write(0x30, enabled?1:0);
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/* set all pins to input to start with */
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for (i=0xe0;i<0xee;i++) {
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ali_write(i, 1);
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}
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for (i=0xf5;i<0xfe;i++) {
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ali_write(i, 1);
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}
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ALI_CLOSE();
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}
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void ali512x_cio_function(int pin, int special, int inv, int input)
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{
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u8 data;
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u8 addr;
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/* valid pins are 10-17, 20-25 and 30-37 */
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if (pin >= 10 && pin <= 17) {
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addr = 0xe0+(pin-10);
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} else if (pin >= 20 && pin <= 25) {
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addr = 0xe8+(pin-20);
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} else if (pin >= 30 && pin <= 37) {
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addr = 0xf5+(pin-30);
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} else {
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return;
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}
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ALI_OPEN();
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ALI_SELDEV(8);
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ali_write(0x03, 0x03); /* Disable CIO data register */
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data=0;
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if (special) {
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data |= 0x08;
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} else {
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if (inv) {
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data |= 0x02;
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}
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if (input) {
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data |= 0x01;
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}
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}
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ali_write(addr, data);
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ALI_CLOSE();
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}
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void ali512x_cio_out(int pin, int value)
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{
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u8 reg;
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u8 data;
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u8 bit;
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/* valid pins are 10-17, 20-25 and 30-37 */
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if (pin >= 10 && pin <= 17) {
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reg = 1;
|
|||
|
|
pin -= 10;
|
|||
|
|
} else if (pin >= 20 && pin <= 25) {
|
|||
|
|
reg = 2;
|
|||
|
|
pin -= 20;
|
|||
|
|
} else if (pin >= 30 && pin <= 37) {
|
|||
|
|
reg = 3;
|
|||
|
|
pin -= 30;
|
|||
|
|
} else {
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
bit = 1 << pin;
|
|||
|
|
|
|||
|
|
ALI_OPEN();
|
|||
|
|
ALI_SELDEV(8);
|
|||
|
|
|
|||
|
|
ali_write(0x03, 0x83); /* Enable CIO data register, use data port at 0xea */
|
|||
|
|
|
|||
|
|
ali_write(0xea, reg); /* select I/O register */
|
|||
|
|
data = ali_read(0xeb);
|
|||
|
|
if (value) {
|
|||
|
|
data |= bit;
|
|||
|
|
} else {
|
|||
|
|
data &= ~bit;
|
|||
|
|
}
|
|||
|
|
ali_write(0xeb, data);
|
|||
|
|
ali_write(0xea, 0); /* select register 0 */
|
|||
|
|
ali_write(0x03, 0x03); /* Disable CIO data register */
|
|||
|
|
ALI_CLOSE();
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
int ali512x_cio_in(int pin)
|
|||
|
|
{
|
|||
|
|
u8 reg;
|
|||
|
|
u8 data;
|
|||
|
|
u8 bit;
|
|||
|
|
|
|||
|
|
/* valid pins are 10-17, 20-25 and 30-37 */
|
|||
|
|
if (pin >= 10 && pin <= 17) {
|
|||
|
|
reg = 1;
|
|||
|
|
pin -= 10;
|
|||
|
|
} else if (pin >= 20 && pin <= 25) {
|
|||
|
|
reg = 2;
|
|||
|
|
pin -= 20;
|
|||
|
|
} else if (pin >= 30 && pin <= 37) {
|
|||
|
|
reg = 3;
|
|||
|
|
pin -= 30;
|
|||
|
|
} else {
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
bit = 1 << pin;
|
|||
|
|
|
|||
|
|
ALI_OPEN();
|
|||
|
|
ALI_SELDEV(8);
|
|||
|
|
|
|||
|
|
ali_write(0x03, 0x83); /* Enable CIO data register, use data port at 0xea */
|
|||
|
|
|
|||
|
|
ali_write(0xea, reg); /* select I/O register */
|
|||
|
|
data = ali_read(0xeb);
|
|||
|
|
ali_write(0xea, 0); /* select register 0 */
|
|||
|
|
ali_write(0x03, 0x03); /* Disable CIO data register */
|
|||
|
|
ALI_CLOSE();
|
|||
|
|
|
|||
|
|
return data & bit;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|