2015-07-25 17:46:26 +00:00
|
|
|
#
|
|
|
|
|
# I2C subsystem configuration
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
menu "I2C support"
|
|
|
|
|
|
2015-01-13 03:44:35 +00:00
|
|
|
config DM_I2C
|
|
|
|
|
bool "Enable Driver Model for I2C drivers"
|
|
|
|
|
depends on DM
|
|
|
|
|
help
|
2015-03-31 16:57:17 +00:00
|
|
|
Enable driver model for I2C. The I2C uclass interface: probe, read,
|
|
|
|
|
write and speed, is implemented with the bus drivers operations,
|
|
|
|
|
which provide methods for bus setting and data transfer. Each chip
|
|
|
|
|
device (bus child) info is kept as parent platdata. The interface
|
|
|
|
|
is defined in include/i2c.h. When i2c bus driver supports the i2c
|
|
|
|
|
uclass, but the device drivers not, then DM_I2C_COMPAT config can
|
|
|
|
|
be used as compatibility layer.
|
2015-01-13 03:44:36 +00:00
|
|
|
|
2015-02-13 19:20:48 +00:00
|
|
|
config DM_I2C_COMPAT
|
|
|
|
|
bool "Enable I2C compatibility layer"
|
|
|
|
|
depends on DM
|
|
|
|
|
help
|
|
|
|
|
Enable old-style I2C functions for compatibility with existing code.
|
|
|
|
|
This option can be enabled as a temporary measure to avoid needing
|
|
|
|
|
to convert all code for a board in a single commit. It should not
|
|
|
|
|
be enabled for any board in an official release.
|
|
|
|
|
|
2015-08-03 14:19:23 +00:00
|
|
|
config I2C_CROS_EC_TUNNEL
|
|
|
|
|
tristate "Chrome OS EC tunnel I2C bus"
|
|
|
|
|
depends on CROS_EC
|
|
|
|
|
help
|
|
|
|
|
This provides an I2C bus that will tunnel i2c commands through to
|
|
|
|
|
the other side of the Chrome OS EC to the I2C bus connected there.
|
|
|
|
|
This will work whatever the interface used to talk to the EC (SPI,
|
|
|
|
|
I2C or LPC). Some Chromebooks use this when the hardware design
|
|
|
|
|
does not allow direct access to the main PMIC from the AP.
|
|
|
|
|
|
2015-08-03 14:19:24 +00:00
|
|
|
config I2C_CROS_EC_LDO
|
|
|
|
|
bool "Provide access to LDOs on the Chrome OS EC"
|
|
|
|
|
depends on CROS_EC
|
|
|
|
|
---help---
|
|
|
|
|
On many Chromebooks the main PMIC is inaccessible to the AP. This is
|
|
|
|
|
often dealt with by using an I2C pass-through interface provided by
|
|
|
|
|
the EC. On some unfortunate models (e.g. Spring) the pass-through
|
|
|
|
|
is not available, and an LDO message is available instead. This
|
|
|
|
|
option enables a driver which provides very basic access to those
|
|
|
|
|
regulators, via the EC. We implement this as an I2C bus which
|
|
|
|
|
emulates just the TPS65090 messages we know about. This is done to
|
|
|
|
|
avoid duplicating the logic in the TPS65090 regulator driver for
|
|
|
|
|
enabling/disabling an LDO.
|
2015-08-03 14:19:23 +00:00
|
|
|
|
2017-03-21 11:08:25 +00:00
|
|
|
config I2C_SET_DEFAULT_BUS_NUM
|
|
|
|
|
bool "Set default I2C bus number"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Set default number of I2C bus to be accessed. This option provides
|
|
|
|
|
behaviour similar to old (i.e. pre DM) I2C bus driver.
|
|
|
|
|
|
|
|
|
|
config I2C_DEFAULT_BUS_NUMBER
|
|
|
|
|
hex "I2C default bus number"
|
|
|
|
|
depends on I2C_SET_DEFAULT_BUS_NUM
|
|
|
|
|
default 0x0
|
|
|
|
|
help
|
|
|
|
|
Number of default I2C bus to use
|
|
|
|
|
|
2015-03-31 16:57:18 +00:00
|
|
|
config DM_I2C_GPIO
|
|
|
|
|
bool "Enable Driver Model for software emulated I2C bus driver"
|
|
|
|
|
depends on DM_I2C && DM_GPIO
|
|
|
|
|
help
|
|
|
|
|
Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
|
|
|
|
|
configuration is given by the device tree. Kernel-style device tree
|
|
|
|
|
bindings are supported.
|
|
|
|
|
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
|
|
|
|
|
|
2016-06-20 05:22:38 +00:00
|
|
|
config SYS_I2C_AT91
|
|
|
|
|
bool "Atmel I2C driver"
|
|
|
|
|
depends on DM_I2C && ARCH_AT91
|
|
|
|
|
help
|
|
|
|
|
Add support for the Atmel I2C driver. A serious problem is that there
|
|
|
|
|
is no documented way to issue repeated START conditions for more than
|
|
|
|
|
two messages, as needed to support combined I2C messages. Use the
|
|
|
|
|
i2c-gpio driver unless your system can cope with this limitation.
|
|
|
|
|
Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
|
|
|
|
|
|
2016-04-25 06:31:09 +00:00
|
|
|
config SYS_I2C_FSL
|
|
|
|
|
bool "Freescale I2C bus driver"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
|
|
|
|
|
MPC85xx processors.
|
|
|
|
|
|
2015-12-28 17:47:11 +00:00
|
|
|
config SYS_I2C_CADENCE
|
|
|
|
|
tristate "Cadence I2C Controller"
|
|
|
|
|
depends on DM_I2C && (ARCH_ZYNQ || ARM64)
|
|
|
|
|
help
|
|
|
|
|
Say yes here to select Cadence I2C Host Controller. This controller is
|
|
|
|
|
e.g. used by Xilinx Zynq.
|
|
|
|
|
|
2016-04-28 07:47:17 +00:00
|
|
|
config SYS_I2C_DW
|
|
|
|
|
bool "Designware I2C Controller"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Say yes here to select the Designware I2C Host Controller. This
|
|
|
|
|
controller is used in various SoCs, e.g. the ST SPEAr, Altera
|
|
|
|
|
SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
|
|
|
|
|
|
2016-04-28 07:47:19 +00:00
|
|
|
config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
|
|
|
|
|
bool "DW I2C Enable Status Register not supported"
|
|
|
|
|
depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
|
|
|
|
|
TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Some versions of the Designware I2C controller do not support the
|
|
|
|
|
enable status register. This config option can be enabled in such
|
|
|
|
|
cases.
|
|
|
|
|
|
2017-04-17 19:00:30 +00:00
|
|
|
config SYS_I2C_ASPEED
|
|
|
|
|
bool "Aspeed I2C Controller"
|
|
|
|
|
depends on DM_I2C && ARCH_ASPEED
|
|
|
|
|
help
|
|
|
|
|
Say yes here to select Aspeed I2C Host Controller. The driver
|
|
|
|
|
supports AST2500 and AST2400 controllers, but is very limited.
|
|
|
|
|
Only single master mode is supported and only byte-by-byte
|
|
|
|
|
synchronous reads and writes are supported, no Pool Buffers or DMA.
|
|
|
|
|
|
2016-01-17 23:11:44 +00:00
|
|
|
config SYS_I2C_INTEL
|
|
|
|
|
bool "Intel I2C/SMBUS driver"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Add support for the Intel SMBUS driver. So far this driver is just
|
|
|
|
|
a stub which perhaps some basic init. There is no implementation of
|
|
|
|
|
the I2C API meaning that any I2C operations will immediately fail
|
|
|
|
|
for now.
|
|
|
|
|
|
2017-02-24 01:54:18 +00:00
|
|
|
config SYS_I2C_IMX_LPI2C
|
|
|
|
|
bool "NXP i.MX LPI2C driver"
|
|
|
|
|
help
|
|
|
|
|
Add support for the NXP i.MX LPI2C driver.
|
|
|
|
|
|
2017-10-29 09:09:00 +00:00
|
|
|
config SYS_I2C_MESON
|
|
|
|
|
bool "Amlogic Meson I2C driver"
|
|
|
|
|
depends on DM_I2C && ARCH_MESON
|
|
|
|
|
help
|
2017-11-26 16:40:54 +00:00
|
|
|
Add support for the I2C controller available in Amlogic Meson
|
|
|
|
|
SoCs. The controller supports programmable bus speed including
|
|
|
|
|
standard (100kbits/s) and fast (400kbit/s) speed and allows the
|
|
|
|
|
software to define a flexible format of the bit streams. It has an
|
|
|
|
|
internal buffer holding up to 8 bytes for transfers and supports
|
|
|
|
|
both 7-bit and 10-bit addresses.
|
2017-10-29 09:09:00 +00:00
|
|
|
|
2016-12-05 23:00:57 +00:00
|
|
|
config SYS_I2C_MXC
|
|
|
|
|
bool "NXP i.MX I2C driver"
|
|
|
|
|
depends on MX6
|
|
|
|
|
help
|
|
|
|
|
Add support for the NXP i.MX I2C driver. This supports upto for bus
|
|
|
|
|
channels and operating on standard mode upto 100 kbits/s and fast
|
|
|
|
|
mode upto 400 kbits/s.
|
|
|
|
|
|
2017-08-07 18:11:34 +00:00
|
|
|
config SYS_I2C_OMAP24XX
|
|
|
|
|
bool "TI OMAP2+ I2C driver"
|
|
|
|
|
depends on ARCH_OMAP2PLUS
|
|
|
|
|
help
|
|
|
|
|
Add support for the OMAP2+ I2C driver.
|
|
|
|
|
|
2018-01-24 21:21:21 +00:00
|
|
|
if SYS_I2C_OMAP24XX
|
|
|
|
|
config SYS_OMAP24_I2C_SLAVE
|
|
|
|
|
int "I2C Slave addr channel 0"
|
|
|
|
|
default 1
|
|
|
|
|
help
|
|
|
|
|
OMAP24xx I2C Slave address channel 0
|
|
|
|
|
|
|
|
|
|
config SYS_OMAP24_I2C_SPEED
|
|
|
|
|
int "I2C Slave channel 0 speed"
|
|
|
|
|
default 100000
|
|
|
|
|
help
|
|
|
|
|
OMAP24xx Slave speed channel 0
|
|
|
|
|
endif
|
|
|
|
|
|
2017-11-28 07:02:27 +00:00
|
|
|
config SYS_I2C_RCAR_IIC
|
|
|
|
|
bool "Renesas RCar Gen3 IIC driver"
|
2018-02-17 01:17:40 +00:00
|
|
|
depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
|
2017-11-28 07:02:27 +00:00
|
|
|
help
|
|
|
|
|
Support for Renesas RCar Gen3 IIC controller.
|
|
|
|
|
|
2015-08-30 22:55:39 +00:00
|
|
|
config SYS_I2C_ROCKCHIP
|
|
|
|
|
bool "Rockchip I2C driver"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Add support for the Rockchip I2C driver. This is used with various
|
|
|
|
|
Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
|
|
|
|
|
have several I2C ports and all are provided, controled by the
|
|
|
|
|
device tree.
|
|
|
|
|
|
2015-03-06 20:19:04 +00:00
|
|
|
config SYS_I2C_SANDBOX
|
|
|
|
|
bool "Sandbox I2C driver"
|
|
|
|
|
depends on SANDBOX && DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Enable I2C support for sandbox. This is an emulation of a real I2C
|
|
|
|
|
bus. Devices can be attached to the bus using the device tree
|
2017-02-11 03:39:55 +00:00
|
|
|
which specifies the driver to use. See sandbox.dts as an example.
|
2015-03-06 20:19:04 +00:00
|
|
|
|
2017-01-09 05:47:52 +00:00
|
|
|
config SYS_I2C_S3C24X0
|
|
|
|
|
bool "Samsung I2C driver"
|
|
|
|
|
depends on ARCH_EXYNOS4 && DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Support for Samsung I2C controller as Samsung SoCs.
|
2015-03-06 20:19:04 +00:00
|
|
|
|
2017-08-09 12:45:27 +00:00
|
|
|
config SYS_I2C_STM32F7
|
|
|
|
|
bool "STMicroelectronics STM32F7 I2C support"
|
|
|
|
|
depends on (STM32F7 || STM32H7) && DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Enable this option to add support for STM32 I2C controller
|
|
|
|
|
introduced with STM32F7/H7 SoCs. This I2C controller supports :
|
|
|
|
|
_ Slave and master modes
|
|
|
|
|
_ Multimaster capability
|
|
|
|
|
_ Standard-mode (up to 100 kHz)
|
|
|
|
|
_ Fast-mode (up to 400 kHz)
|
|
|
|
|
_ Fast-mode Plus (up to 1 MHz)
|
|
|
|
|
_ 7-bit and 10-bit addressing mode
|
|
|
|
|
_ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
|
|
|
|
|
_ All 7-bit addresses acknowledge mode
|
|
|
|
|
_ General call
|
|
|
|
|
_ Programmable setup and hold times
|
|
|
|
|
_ Easy to use event management
|
|
|
|
|
_ Optional clock stretching
|
|
|
|
|
_ Software reset
|
|
|
|
|
|
2015-01-13 03:44:36 +00:00
|
|
|
config SYS_I2C_UNIPHIER
|
|
|
|
|
bool "UniPhier I2C driver"
|
|
|
|
|
depends on ARCH_UNIPHIER && DM_I2C
|
|
|
|
|
default y
|
|
|
|
|
help
|
2015-05-29 08:30:01 +00:00
|
|
|
Support for UniPhier I2C controller driver. This I2C controller
|
|
|
|
|
is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
|
2015-01-13 03:44:37 +00:00
|
|
|
|
|
|
|
|
config SYS_I2C_UNIPHIER_F
|
|
|
|
|
bool "UniPhier FIFO-builtin I2C driver"
|
|
|
|
|
depends on ARCH_UNIPHIER && DM_I2C
|
|
|
|
|
default y
|
|
|
|
|
help
|
2015-05-29 08:30:01 +00:00
|
|
|
Support for UniPhier FIFO-builtin I2C controller driver.
|
2015-01-13 03:44:37 +00:00
|
|
|
This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
|
2015-08-03 14:19:21 +00:00
|
|
|
|
2016-07-21 09:57:10 +00:00
|
|
|
config SYS_I2C_MVTWSI
|
|
|
|
|
bool "Marvell I2C driver"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Support for Marvell I2C controllers as used on the orion5x and
|
|
|
|
|
kirkwood SoC families.
|
|
|
|
|
|
2016-08-08 17:28:27 +00:00
|
|
|
config TEGRA186_BPMP_I2C
|
|
|
|
|
bool "Enable Tegra186 BPMP-based I2C driver"
|
|
|
|
|
depends on TEGRA186_BPMP
|
|
|
|
|
help
|
|
|
|
|
Support for Tegra I2C controllers managed by the BPMP (Boot and
|
|
|
|
|
Power Management Processor). On Tegra186, some I2C controllers are
|
|
|
|
|
directly controlled by the main CPU, whereas others are controlled
|
|
|
|
|
by the BPMP, and can only be accessed by the main CPU via IPC
|
|
|
|
|
requests to the BPMP. This driver covers the latter case.
|
|
|
|
|
|
2017-08-11 11:39:34 +00:00
|
|
|
config SYS_I2C_BUS_MAX
|
|
|
|
|
int "Max I2C busses"
|
|
|
|
|
depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
|
|
|
|
|
default 2 if TI816X
|
|
|
|
|
default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
|
|
|
|
|
default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
|
|
|
|
|
default 5 if OMAP54XX
|
|
|
|
|
help
|
|
|
|
|
Define the maximum number of available I2C buses.
|
|
|
|
|
|
2018-02-16 13:37:17 +00:00
|
|
|
config SYS_I2C_ZYNQ
|
|
|
|
|
bool "Xilinx I2C driver"
|
|
|
|
|
depends on ARCH_ZYNQMP || ARCH_ZYNQ
|
|
|
|
|
help
|
|
|
|
|
Support for Xilinx I2C controller.
|
|
|
|
|
|
2018-02-16 13:37:19 +00:00
|
|
|
config SYS_I2C_ZYNQ_SLAVE
|
|
|
|
|
hex "Set slave addr"
|
|
|
|
|
depends on SYS_I2C_ZYNQ
|
|
|
|
|
default 0
|
|
|
|
|
help
|
|
|
|
|
Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
|
|
|
|
|
|
2018-02-16 13:37:20 +00:00
|
|
|
config SYS_I2C_ZYNQ_SPEED
|
|
|
|
|
int "Set I2C speed"
|
|
|
|
|
depends on SYS_I2C_ZYNQ
|
|
|
|
|
default 100000
|
|
|
|
|
help
|
|
|
|
|
Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
|
|
|
|
|
|
2018-02-16 13:37:22 +00:00
|
|
|
config ZYNQ_I2C0
|
|
|
|
|
bool "Xilinx I2C0 controller"
|
|
|
|
|
depends on SYS_I2C_ZYNQ
|
|
|
|
|
help
|
|
|
|
|
Enable Xilinx I2C0 controller.
|
|
|
|
|
|
|
|
|
|
config ZYNQ_I2C1
|
|
|
|
|
bool "Xilinx I2C1 controller"
|
|
|
|
|
depends on SYS_I2C_ZYNQ
|
|
|
|
|
help
|
|
|
|
|
Enable Xilinx I2C1 controller.
|
|
|
|
|
|
2018-01-15 10:08:11 +00:00
|
|
|
config SYS_I2C_IHS
|
|
|
|
|
bool "gdsys IHS I2C driver"
|
|
|
|
|
depends on DM_I2C
|
|
|
|
|
help
|
|
|
|
|
Support for gdsys IHS I2C driver on FPGA bus.
|
|
|
|
|
|
2015-08-03 14:19:21 +00:00
|
|
|
source "drivers/i2c/muxes/Kconfig"
|
2015-07-25 17:46:26 +00:00
|
|
|
|
|
|
|
|
endmenu
|
