68 lines
2.2 KiB
Plaintext
68 lines
2.2 KiB
Plaintext
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RK3368 dynamic memory controller driver
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=======================================
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The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
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during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
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the following key configuration data:
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(a) a target-frequency (i.e. operating point) for the memory operation
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(b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
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(c) a memory-schedule (i.e. mapping from physical addresses to the address
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pins of the memory bus)
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Required properties
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-------------------
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- compatible: "rockchip,rk3368-dmc"
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- reg
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protocol controller (PCTL) address and PHY controller (DDRPHY) address
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- rockchip,ddr-speed-bin
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the DDR3 device's speed-bin (as specified according to JESD-79)
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DDR3_800D (5-5-5)
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DDR3_800E (6-6-6)
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DDR3_1066E (6-6-6)
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DDR3_1066F (7-7-7)
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DDR3_1066G (8-8-8)
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DDR3_1333F (7-7-7)
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DDR3_1333G (8-8-8)
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DDR3_1333H (9-9-9)
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DDR3_1333J (10-10-10)
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DDR3_1600G (8-8-8)
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DDR3_1600H (9-9-9)
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DDR3_1600J (10-10-10)
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DDR3_1600K (11-11-11)
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DDR3_1866J (10-10-10)
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DDR3_1866K (11-11-11)
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DDR3_1866L (12-12-12)
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DDR3_1866M (13-13-13)
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DDR3_2133K (11-11-11)
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DDR3_2133L (12-12-12)
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DDR3_2133M (13-13-13)
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DDR3_2133N (14-14-14)
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- rockchip,ddr-frequency:
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target DDR clock frequency in Hz (not all frequencies may be supported,
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as there's some cooperation from the clock-driver required)
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- rockchip,memory-schedule:
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controls the decoding of physical addresses to DRAM addressing (i.e. how
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the physical address maps onto the address pins/chip-select of the device)
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DMC_MSCH_CBDR: column -> bank -> device -> row
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DMC_MSCH_CBRD: column -> band -> row -> device
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DMC_MSCH_CRBD: column -> row -> band -> device
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Example (for DDR3-1600K and 800MHz)
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-----------------------------------
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#include <dt-bindings/memory/rk3368-dmc.h>
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dmc: dmc@ff610000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3368-dmc";
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reg = <0 0xff610000 0 0x400
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0 0xff620000 0 0x400>;
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};
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&dmc {
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rockchip,ddr-speed-bin = <DDR3_1600K>;
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rockchip,ddr-frequency = <800000000>;
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rockchip,memory-schedule = <DMC_MSCH_CBRD>;
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};
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