21 lines
428 B
C
21 lines
428 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2019 Xilinx, Inc,
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* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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*/
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#ifndef _VERSALPL_H_
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#define _VERSALPL_H_
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#include <xilinx.h>
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#define VERSAL_PM_LOAD_PDI 0x701
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#define VERSAL_PM_PDI_TYPE 0xF
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extern struct xilinx_fpga_op versal_op;
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#define XILINX_VERSAL_DESC \
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{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
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#endif /* _VERSALPL_H_ */
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