forked from Minki/linux
fffaa65dc4
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
750 lines
19 KiB
Plaintext
750 lines
19 KiB
Plaintext
/*
|
|
* Copyright 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include "imx6sl-pinfunc.h"
|
|
#include <dt-bindings/clock/imx6sl-clock.h>
|
|
|
|
/ {
|
|
aliases {
|
|
gpio0 = &gpio1;
|
|
gpio1 = &gpio2;
|
|
gpio2 = &gpio3;
|
|
gpio3 = &gpio4;
|
|
gpio4 = &gpio5;
|
|
serial0 = &uart1;
|
|
serial1 = &uart2;
|
|
serial2 = &uart3;
|
|
serial3 = &uart4;
|
|
serial4 = &uart5;
|
|
spi0 = &ecspi1;
|
|
spi1 = &ecspi2;
|
|
spi2 = &ecspi3;
|
|
spi3 = &ecspi4;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a9";
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@00a01000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
reg = <0x00a01000 0x1000>,
|
|
<0x00a00100 0x100>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ckil {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
osc {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&intc>;
|
|
ranges;
|
|
|
|
L2: l2-cache@00a02000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x00a02000 0x1000>;
|
|
interrupts = <0 92 0x04>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
arm,tag-latency = <4 2 3>;
|
|
arm,data-latency = <4 2 3>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 94 0x04>;
|
|
};
|
|
|
|
aips1: aips-bus@02000000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02000000 0x100000>;
|
|
ranges;
|
|
|
|
spba: spba-bus@02000000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02000000 0x40000>;
|
|
ranges;
|
|
|
|
spdif: spdif@02004000 {
|
|
reg = <0x02004000 0x4000>;
|
|
interrupts = <0 52 0x04>;
|
|
};
|
|
|
|
ecspi1: ecspi@02008000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02008000 0x4000>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_ECSPI1>,
|
|
<&clks IMX6SL_CLK_ECSPI1>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi2: ecspi@0200c000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x0200c000 0x4000>;
|
|
interrupts = <0 32 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_ECSPI2>,
|
|
<&clks IMX6SL_CLK_ECSPI2>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi3: ecspi@02010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02010000 0x4000>;
|
|
interrupts = <0 33 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_ECSPI3>,
|
|
<&clks IMX6SL_CLK_ECSPI3>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi4: ecspi@02014000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x02014000 0x4000>;
|
|
interrupts = <0 34 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_ECSPI4>,
|
|
<&clks IMX6SL_CLK_ECSPI4>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@02018000 {
|
|
compatible = "fsl,imx6sl-uart",
|
|
"fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02018000 0x4000>;
|
|
interrupts = <0 30 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_UART>,
|
|
<&clks IMX6SL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@02020000 {
|
|
compatible = "fsl,imx6sl-uart",
|
|
"fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02020000 0x4000>;
|
|
interrupts = <0 26 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_UART>,
|
|
<&clks IMX6SL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@02024000 {
|
|
compatible = "fsl,imx6sl-uart",
|
|
"fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02024000 0x4000>;
|
|
interrupts = <0 27 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_UART>,
|
|
<&clks IMX6SL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi1: ssi@02028000 {
|
|
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
|
|
reg = <0x02028000 0x4000>;
|
|
interrupts = <0 46 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_SSI1>;
|
|
dmas = <&sdma 37 1 0>,
|
|
<&sdma 38 1 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi2: ssi@0202c000 {
|
|
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
|
|
reg = <0x0202c000 0x4000>;
|
|
interrupts = <0 47 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_SSI2>;
|
|
dmas = <&sdma 41 1 0>,
|
|
<&sdma 42 1 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssi3: ssi@02030000 {
|
|
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
|
|
reg = <0x02030000 0x4000>;
|
|
interrupts = <0 48 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_SSI3>;
|
|
dmas = <&sdma 45 1 0>,
|
|
<&sdma 46 1 0>;
|
|
dma-names = "rx", "tx";
|
|
fsl,fifo-depth = <15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@02034000 {
|
|
compatible = "fsl,imx6sl-uart",
|
|
"fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02034000 0x4000>;
|
|
interrupts = <0 28 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_UART>,
|
|
<&clks IMX6SL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@02038000 {
|
|
compatible = "fsl,imx6sl-uart",
|
|
"fsl,imx6q-uart", "fsl,imx21-uart";
|
|
reg = <0x02038000 0x4000>;
|
|
interrupts = <0 29 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_UART>,
|
|
<&clks IMX6SL_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pwm1: pwm@02080000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02080000 0x4000>;
|
|
interrupts = <0 83 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_PWM1>,
|
|
<&clks IMX6SL_CLK_PWM1>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
pwm2: pwm@02084000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02084000 0x4000>;
|
|
interrupts = <0 84 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_PWM2>,
|
|
<&clks IMX6SL_CLK_PWM2>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
pwm3: pwm@02088000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02088000 0x4000>;
|
|
interrupts = <0 85 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_PWM3>,
|
|
<&clks IMX6SL_CLK_PWM3>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
pwm4: pwm@0208c000 {
|
|
#pwm-cells = <2>;
|
|
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
|
|
reg = <0x0208c000 0x4000>;
|
|
interrupts = <0 86 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_PWM4>,
|
|
<&clks IMX6SL_CLK_PWM4>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpt: gpt@02098000 {
|
|
compatible = "fsl,imx6sl-gpt";
|
|
reg = <0x02098000 0x4000>;
|
|
interrupts = <0 55 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_GPT>,
|
|
<&clks IMX6SL_CLK_GPT_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpio1: gpio@0209c000 {
|
|
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
|
reg = <0x0209c000 0x4000>;
|
|
interrupts = <0 66 0x04 0 67 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@020a0000 {
|
|
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a0000 0x4000>;
|
|
interrupts = <0 68 0x04 0 69 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@020a4000 {
|
|
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a4000 0x4000>;
|
|
interrupts = <0 70 0x04 0 71 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@020a8000 {
|
|
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a8000 0x4000>;
|
|
interrupts = <0 72 0x04 0 73 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@020ac000 {
|
|
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020ac000 0x4000>;
|
|
interrupts = <0 74 0x04 0 75 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
kpp: kpp@020b8000 {
|
|
reg = <0x020b8000 0x4000>;
|
|
interrupts = <0 82 0x04>;
|
|
};
|
|
|
|
wdog1: wdog@020bc000 {
|
|
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020bc000 0x4000>;
|
|
interrupts = <0 80 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
|
};
|
|
|
|
wdog2: wdog@020c0000 {
|
|
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020c0000 0x4000>;
|
|
interrupts = <0 81 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clks: ccm@020c4000 {
|
|
compatible = "fsl,imx6sl-ccm";
|
|
reg = <0x020c4000 0x4000>;
|
|
interrupts = <0 87 0x04 0 88 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
anatop: anatop@020c8000 {
|
|
compatible = "fsl,imx6sl-anatop",
|
|
"fsl,imx6q-anatop",
|
|
"syscon", "simple-bus";
|
|
reg = <0x020c8000 0x1000>;
|
|
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
|
|
|
|
regulator-1p1@110 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd1p1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1375000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x110>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <4>;
|
|
anatop-min-voltage = <800000>;
|
|
anatop-max-voltage = <1375000>;
|
|
};
|
|
|
|
regulator-3p0@120 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd3p0";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <3150000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x120>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2625000>;
|
|
anatop-max-voltage = <3400000>;
|
|
};
|
|
|
|
regulator-2p5@130 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd2p5";
|
|
regulator-min-microvolt = <2100000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x130>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2100000>;
|
|
anatop-max-voltage = <2850000>;
|
|
};
|
|
|
|
reg_arm: regulator-vddcore@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "cpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <0>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <24>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_pu: regulator-vddpu@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <9>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <26>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_soc: regulator-vddsoc@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddsoc";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <18>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <28>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
};
|
|
|
|
usbphy1: usbphy@020c9000 {
|
|
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020c9000 0x1000>;
|
|
interrupts = <0 44 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USBPHY1>;
|
|
};
|
|
|
|
usbphy2: usbphy@020ca000 {
|
|
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020ca000 0x1000>;
|
|
interrupts = <0 45 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USBPHY2>;
|
|
};
|
|
|
|
snvs@020cc000 {
|
|
compatible = "fsl,sec-v4.0-mon", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x020cc000 0x4000>;
|
|
|
|
snvs-rtc-lp@34 {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
reg = <0x34 0x58>;
|
|
interrupts = <0 19 0x04 0 20 0x04>;
|
|
};
|
|
};
|
|
|
|
epit1: epit@020d0000 {
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <0 56 0x04>;
|
|
};
|
|
|
|
epit2: epit@020d4000 {
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <0 57 0x04>;
|
|
};
|
|
|
|
src: src@020d8000 {
|
|
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <0 91 0x04 0 96 0x04>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@020dc000 {
|
|
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupts = <0 89 0x04>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@020e0000 {
|
|
compatible = "fsl,imx6sl-iomuxc-gpr",
|
|
"fsl,imx6q-iomuxc-gpr", "syscon";
|
|
reg = <0x020e0000 0x38>;
|
|
};
|
|
|
|
iomuxc: iomuxc@020e0000 {
|
|
compatible = "fsl,imx6sl-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
};
|
|
|
|
csi: csi@020e4000 {
|
|
reg = <0x020e4000 0x4000>;
|
|
interrupts = <0 7 0x04>;
|
|
};
|
|
|
|
spdc: spdc@020e8000 {
|
|
reg = <0x020e8000 0x4000>;
|
|
interrupts = <0 6 0x04>;
|
|
};
|
|
|
|
sdma: sdma@020ec000 {
|
|
compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
|
|
reg = <0x020ec000 0x4000>;
|
|
interrupts = <0 2 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_SDMA>,
|
|
<&clks IMX6SL_CLK_SDMA>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
/* imx6sl reuses imx6q sdma firmware */
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
|
};
|
|
|
|
pxp: pxp@020f0000 {
|
|
reg = <0x020f0000 0x4000>;
|
|
interrupts = <0 98 0x04>;
|
|
};
|
|
|
|
epdc: epdc@020f4000 {
|
|
reg = <0x020f4000 0x4000>;
|
|
interrupts = <0 97 0x04>;
|
|
};
|
|
|
|
lcdif: lcdif@020f8000 {
|
|
reg = <0x020f8000 0x4000>;
|
|
interrupts = <0 39 0x04>;
|
|
};
|
|
|
|
dcp: dcp@020fc000 {
|
|
reg = <0x020fc000 0x4000>;
|
|
interrupts = <0 99 0x04>;
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@02100000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
usbotg1: usb@02184000 {
|
|
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <0 43 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg2: usb@02184200 {
|
|
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <0 42 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh: usb@02184400 {
|
|
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
|
|
reg = <0x02184400 0x200>;
|
|
interrupts = <0 40 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@02184800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x02184800 0x200>;
|
|
clocks = <&clks IMX6SL_CLK_USBOH3>;
|
|
};
|
|
|
|
fec: ethernet@02188000 {
|
|
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupts = <0 114 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_ENET_REF>,
|
|
<&clks IMX6SL_CLK_ENET_REF>;
|
|
clock-names = "ipg", "ahb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@02190000 {
|
|
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <0 22 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USDHC1>,
|
|
<&clks IMX6SL_CLK_USDHC1>,
|
|
<&clks IMX6SL_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@02194000 {
|
|
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <0 23 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USDHC2>,
|
|
<&clks IMX6SL_CLK_USDHC2>,
|
|
<&clks IMX6SL_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: usdhc@02198000 {
|
|
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <0 24 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USDHC3>,
|
|
<&clks IMX6SL_CLK_USDHC3>,
|
|
<&clks IMX6SL_CLK_USDHC3>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc4: usdhc@0219c000 {
|
|
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
|
|
reg = <0x0219c000 0x4000>;
|
|
interrupts = <0 25 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_USDHC4>,
|
|
<&clks IMX6SL_CLK_USDHC4>,
|
|
<&clks IMX6SL_CLK_USDHC4>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@021a0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <0 36 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@021a4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <0 37 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@021a8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <0 38 0x04>;
|
|
clocks = <&clks IMX6SL_CLK_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmdc: mmdc@021b0000 {
|
|
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
};
|
|
|
|
rngb: rngb@021b4000 {
|
|
reg = <0x021b4000 0x4000>;
|
|
interrupts = <0 5 0x04>;
|
|
};
|
|
|
|
weim: weim@021b8000 {
|
|
reg = <0x021b8000 0x4000>;
|
|
interrupts = <0 14 0x04>;
|
|
};
|
|
|
|
ocotp: ocotp@021bc000 {
|
|
compatible = "fsl,imx6sl-ocotp";
|
|
reg = <0x021bc000 0x4000>;
|
|
};
|
|
|
|
audmux: audmux@021d8000 {
|
|
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
|
|
reg = <0x021d8000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|