ffae8475b9
In order to implement clock switching for the CLKID_CPU_CLK and CLKID_CPUB_CLK, notifiers are added on specific points of the clock tree : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This for each cluster, a single one for G12A, two for G12B. Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT, to be used as "parking" clock in a safe clock frequency. A notifier is added on each cpu_clk_premux0 to detech when CCF want to change the frequency of the cpu_clk_dyn tree. In this notifier, the cpu_clk_premux1 tree is configured to use the xtal clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF updates the cpu_clk_premux0 tree. A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to change the PLL clock source of the cpu_clk. In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF updates the sys_pll/sys1_pll frequency. A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn, add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other notofiers change propagate before changing the cpu_clk_premux0 and sys_pll clock trees. This notifier set permits switching the cpu_clk / cpub_clk without any glitches and using a safe parking clock while switching between sub-GHz clocks using the cpu_clk_dyn tree. This setup has been tested and validated on the Amlogic G12A and G12B SoCs running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
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.. | ||
axg-aoclk.c | ||
axg-aoclk.h | ||
axg-audio.c | ||
axg-audio.h | ||
axg.c | ||
axg.h | ||
clk-cpu-dyndiv.c | ||
clk-cpu-dyndiv.h | ||
clk-dualdiv.c | ||
clk-dualdiv.h | ||
clk-mpll.c | ||
clk-mpll.h | ||
clk-phase.c | ||
clk-phase.h | ||
clk-pll.c | ||
clk-pll.h | ||
clk-regmap.c | ||
clk-regmap.h | ||
g12a-aoclk.c | ||
g12a-aoclk.h | ||
g12a.c | ||
g12a.h | ||
gxbb-aoclk.c | ||
gxbb-aoclk.h | ||
gxbb.c | ||
gxbb.h | ||
Kconfig | ||
Makefile | ||
meson8b.c | ||
meson8b.h | ||
meson-aoclk.c | ||
meson-aoclk.h | ||
meson-eeclk.c | ||
meson-eeclk.h | ||
parm.h | ||
sclk-div.c | ||
sclk-div.h | ||
vid-pll-div.c | ||
vid-pll-div.h |