forked from Minki/linux
26da35010c
Geert Uytterhoeven <geert@linux-m68k.org> reported:
> HOSTLD scripts/mod/modpost
> CC arch/sh/kernel/traps_32.o
> arch/sh/kernel/traps_32.c: In function 'do_divide_error':
> arch/sh/kernel/traps_32.c:606:17: error: 'code' may be used uninitialized in this function [-Werror=uninitialized]
> cc1: all warnings being treated as errors
It is clear from inspection that do_divide_error is only called with
TRAP_DIVZERO_ERROR or TRAP_DIVOVF_ERROR, as that is the way
set_exception_table_vec is called. So let gcc know the other cases
should not be considered by returning in all other cases.
This removes the warning and let's the code continue to build.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Fixes: c65626c0cd
("signal/sh: Use force_sig_fault where appropriate")
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
795 lines
18 KiB
C
795 lines
18 KiB
C
/*
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* 'traps.c' handles hardware traps and faults after we have saved some
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* state in 'entry.S'.
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*
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* SuperH version: Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2000 Philipp Rumpf
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* Copyright (C) 2000 David Howells
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* Copyright (C) 2002 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/kallsyms.h>
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#include <linux/io.h>
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#include <linux/bug.h>
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#include <linux/debug_locks.h>
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#include <linux/kdebug.h>
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#include <linux/limits.h>
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#include <linux/sysfs.h>
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#include <linux/uaccess.h>
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#include <linux/perf_event.h>
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#include <linux/sched/task_stack.h>
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#include <asm/alignment.h>
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#include <asm/fpu.h>
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#include <asm/kprobes.h>
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#include <asm/traps.h>
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#include <asm/bl_bit.h>
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#ifdef CONFIG_CPU_SH2
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# define TRAP_RESERVED_INST 4
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# define TRAP_ILLEGAL_SLOT_INST 6
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# define TRAP_ADDRESS_ERROR 9
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# ifdef CONFIG_CPU_SH2A
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# define TRAP_UBC 12
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# define TRAP_FPU_ERROR 13
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# define TRAP_DIVZERO_ERROR 17
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# define TRAP_DIVOVF_ERROR 18
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# endif
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#else
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#define TRAP_RESERVED_INST 12
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#define TRAP_ILLEGAL_SLOT_INST 13
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#endif
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static inline void sign_extend(unsigned int count, unsigned char *dst)
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{
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#ifdef __LITTLE_ENDIAN__
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if ((count == 1) && dst[0] & 0x80) {
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dst[1] = 0xff;
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dst[2] = 0xff;
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dst[3] = 0xff;
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}
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if ((count == 2) && dst[1] & 0x80) {
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dst[2] = 0xff;
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dst[3] = 0xff;
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}
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#else
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if ((count == 1) && dst[3] & 0x80) {
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dst[2] = 0xff;
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dst[1] = 0xff;
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dst[0] = 0xff;
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}
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if ((count == 2) && dst[2] & 0x80) {
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dst[1] = 0xff;
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dst[0] = 0xff;
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}
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#endif
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}
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static struct mem_access user_mem_access = {
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copy_from_user,
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copy_to_user,
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};
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/*
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* handle an instruction that does an unaligned memory access by emulating the
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* desired behaviour
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* - note that PC _may not_ point to the faulting instruction
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* (if that instruction is in a branch delay slot)
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* - return 0 if emulation okay, -EFAULT on existential error
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*/
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static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
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struct mem_access *ma)
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{
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int ret, index, count;
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unsigned long *rm, *rn;
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unsigned char *src, *dst;
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unsigned char __user *srcu, *dstu;
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index = (instruction>>8)&15; /* 0x0F00 */
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rn = ®s->regs[index];
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index = (instruction>>4)&15; /* 0x00F0 */
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rm = ®s->regs[index];
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count = 1<<(instruction&3);
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switch (count) {
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case 1: inc_unaligned_byte_access(); break;
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case 2: inc_unaligned_word_access(); break;
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case 4: inc_unaligned_dword_access(); break;
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case 8: inc_unaligned_multi_access(); break;
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}
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ret = -EFAULT;
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switch (instruction>>12) {
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case 0: /* mov.[bwl] to/from memory via r0+rn */
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if (instruction & 8) {
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/* from memory */
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srcu = (unsigned char __user *)*rm;
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srcu += regs->regs[0];
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 4-count;
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#endif
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if (ma->from(dst, srcu, count))
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goto fetch_fault;
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sign_extend(count, dst);
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} else {
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/* to memory */
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src = (unsigned char *)rm;
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#if !defined(__LITTLE_ENDIAN__)
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src += 4-count;
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#endif
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dstu = (unsigned char __user *)*rn;
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dstu += regs->regs[0];
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if (ma->to(dstu, src, count))
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goto fetch_fault;
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}
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ret = 0;
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break;
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case 1: /* mov.l Rm,@(disp,Rn) */
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src = (unsigned char*) rm;
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dstu = (unsigned char __user *)*rn;
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dstu += (instruction&0x000F)<<2;
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if (ma->to(dstu, src, 4))
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goto fetch_fault;
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ret = 0;
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break;
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case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
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if (instruction & 4)
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*rn -= count;
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src = (unsigned char*) rm;
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dstu = (unsigned char __user *)*rn;
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#if !defined(__LITTLE_ENDIAN__)
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src += 4-count;
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#endif
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if (ma->to(dstu, src, count))
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goto fetch_fault;
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ret = 0;
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break;
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case 5: /* mov.l @(disp,Rm),Rn */
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srcu = (unsigned char __user *)*rm;
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srcu += (instruction & 0x000F) << 2;
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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if (ma->from(dst, srcu, 4))
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goto fetch_fault;
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ret = 0;
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break;
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case 6: /* mov.[bwl] from memory, possibly with post-increment */
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srcu = (unsigned char __user *)*rm;
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if (instruction & 4)
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*rm += count;
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dst = (unsigned char*) rn;
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*(unsigned long*)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 4-count;
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#endif
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if (ma->from(dst, srcu, count))
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goto fetch_fault;
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sign_extend(count, dst);
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ret = 0;
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break;
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case 8:
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switch ((instruction&0xFF00)>>8) {
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case 0x81: /* mov.w R0,@(disp,Rn) */
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src = (unsigned char *) ®s->regs[0];
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#if !defined(__LITTLE_ENDIAN__)
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src += 2;
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#endif
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dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
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dstu += (instruction & 0x000F) << 1;
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if (ma->to(dstu, src, 2))
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goto fetch_fault;
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ret = 0;
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break;
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case 0x85: /* mov.w @(disp,Rm),R0 */
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srcu = (unsigned char __user *)*rm;
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srcu += (instruction & 0x000F) << 1;
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dst = (unsigned char *) ®s->regs[0];
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*(unsigned long *)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 2;
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#endif
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if (ma->from(dst, srcu, 2))
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goto fetch_fault;
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sign_extend(2, dst);
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ret = 0;
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break;
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}
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break;
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case 9: /* mov.w @(disp,PC),Rn */
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srcu = (unsigned char __user *)regs->pc;
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srcu += 4;
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srcu += (instruction & 0x00FF) << 1;
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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#if !defined(__LITTLE_ENDIAN__)
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dst += 2;
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#endif
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if (ma->from(dst, srcu, 2))
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goto fetch_fault;
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sign_extend(2, dst);
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ret = 0;
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break;
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case 0xd: /* mov.l @(disp,PC),Rn */
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srcu = (unsigned char __user *)(regs->pc & ~0x3);
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srcu += 4;
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srcu += (instruction & 0x00FF) << 2;
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dst = (unsigned char *)rn;
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*(unsigned long *)dst = 0;
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if (ma->from(dst, srcu, 4))
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goto fetch_fault;
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ret = 0;
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break;
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}
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return ret;
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fetch_fault:
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/* Argh. Address not only misaligned but also non-existent.
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* Raise an EFAULT and see if it's trapped
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*/
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die_if_no_fixup("Fault in unaligned fixup", regs, 0);
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return -EFAULT;
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}
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/*
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* emulate the instruction in the delay slot
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* - fetches the instruction from PC+2
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*/
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static inline int handle_delayslot(struct pt_regs *regs,
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insn_size_t old_instruction,
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struct mem_access *ma)
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{
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insn_size_t instruction;
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void __user *addr = (void __user *)(regs->pc +
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instruction_size(old_instruction));
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if (copy_from_user(&instruction, addr, sizeof(instruction))) {
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/* the instruction-fetch faulted */
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if (user_mode(regs))
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return -EFAULT;
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/* kernel */
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die("delay-slot-insn faulting in handle_unaligned_delayslot",
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regs, 0);
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}
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return handle_unaligned_ins(instruction, regs, ma);
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}
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/*
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* handle an instruction that does an unaligned memory access
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* - have to be careful of branch delay-slot instructions that fault
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* SH3:
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* - if the branch would be taken PC points to the branch
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* - if the branch would not be taken, PC points to delay-slot
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* SH4:
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* - PC always points to delayed branch
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* - return 0 if handled, -EFAULT if failed (may not return if in kernel)
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*/
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/* Macros to determine offset from current PC for branch instructions */
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/* Explicit type coercion is used to force sign extension where needed */
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#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
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#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
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int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
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struct mem_access *ma, int expected,
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unsigned long address)
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{
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u_int rm;
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int ret, index;
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/*
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* XXX: We can't handle mixed 16/32-bit instructions yet
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*/
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if (instruction_size(instruction) != 2)
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return -EINVAL;
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index = (instruction>>8)&15; /* 0x0F00 */
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rm = regs->regs[index];
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/*
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* Log the unexpected fixups, and then pass them on to perf.
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*
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* We intentionally don't report the expected cases to perf as
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* otherwise the trapped I/O case will skew the results too much
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* to be useful.
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*/
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if (!expected) {
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unaligned_fixups_notify(current, instruction, regs);
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
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regs, address);
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}
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ret = -EFAULT;
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switch (instruction&0xF000) {
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case 0x0000:
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if (instruction==0x000B) {
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/* rts */
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ret = handle_delayslot(regs, instruction, ma);
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if (ret==0)
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regs->pc = regs->pr;
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}
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else if ((instruction&0x00FF)==0x0023) {
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/* braf @Rm */
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ret = handle_delayslot(regs, instruction, ma);
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if (ret==0)
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regs->pc += rm + 4;
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}
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else if ((instruction&0x00FF)==0x0003) {
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/* bsrf @Rm */
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ret = handle_delayslot(regs, instruction, ma);
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if (ret==0) {
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regs->pr = regs->pc + 4;
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regs->pc += rm + 4;
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}
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}
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else {
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/* mov.[bwl] to/from memory via r0+rn */
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goto simple;
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}
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break;
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case 0x1000: /* mov.l Rm,@(disp,Rn) */
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goto simple;
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|
case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
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|
goto simple;
|
|
|
|
case 0x4000:
|
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if ((instruction&0x00FF)==0x002B) {
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|
/* jmp @Rm */
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|
ret = handle_delayslot(regs, instruction, ma);
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if (ret==0)
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regs->pc = rm;
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}
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else if ((instruction&0x00FF)==0x000B) {
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/* jsr @Rm */
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ret = handle_delayslot(regs, instruction, ma);
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if (ret==0) {
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regs->pr = regs->pc + 4;
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regs->pc = rm;
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}
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}
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else {
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/* mov.[bwl] to/from memory via r0+rn */
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goto simple;
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|
}
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break;
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|
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case 0x5000: /* mov.l @(disp,Rm),Rn */
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goto simple;
|
|
|
|
case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
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goto simple;
|
|
|
|
case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
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|
switch (instruction&0x0F00) {
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|
case 0x0100: /* mov.w R0,@(disp,Rm) */
|
|
goto simple;
|
|
case 0x0500: /* mov.w @(disp,Rm),R0 */
|
|
goto simple;
|
|
case 0x0B00: /* bf lab - no delayslot*/
|
|
ret = 0;
|
|
break;
|
|
case 0x0F00: /* bf/s lab */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
|
|
if ((regs->sr & 0x00000001) != 0)
|
|
regs->pc += 4; /* next after slot */
|
|
else
|
|
#endif
|
|
regs->pc += SH_PC_8BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
case 0x0900: /* bt lab - no delayslot */
|
|
ret = 0;
|
|
break;
|
|
case 0x0D00: /* bt/s lab */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
|
|
if ((regs->sr & 0x00000001) == 0)
|
|
regs->pc += 4; /* next after slot */
|
|
else
|
|
#endif
|
|
regs->pc += SH_PC_8BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 0x9000: /* mov.w @(disp,Rm),Rn */
|
|
goto simple;
|
|
|
|
case 0xA000: /* bra label */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0)
|
|
regs->pc += SH_PC_12BIT_OFFSET(instruction);
|
|
break;
|
|
|
|
case 0xB000: /* bsr label */
|
|
ret = handle_delayslot(regs, instruction, ma);
|
|
if (ret==0) {
|
|
regs->pr = regs->pc + 4;
|
|
regs->pc += SH_PC_12BIT_OFFSET(instruction);
|
|
}
|
|
break;
|
|
|
|
case 0xD000: /* mov.l @(disp,Rm),Rn */
|
|
goto simple;
|
|
}
|
|
return ret;
|
|
|
|
/* handle non-delay-slot instruction */
|
|
simple:
|
|
ret = handle_unaligned_ins(instruction, regs, ma);
|
|
if (ret==0)
|
|
regs->pc += instruction_size(instruction);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Handle various address error exceptions:
|
|
* - instruction address error:
|
|
* misaligned PC
|
|
* PC >= 0x80000000 in user mode
|
|
* - data address error (read and write)
|
|
* misaligned data access
|
|
* access to >= 0x80000000 is user mode
|
|
* Unfortuntaly we can't distinguish between instruction address error
|
|
* and data address errors caused by read accesses.
|
|
*/
|
|
asmlinkage void do_address_error(struct pt_regs *regs,
|
|
unsigned long writeaccess,
|
|
unsigned long address)
|
|
{
|
|
unsigned long error_code = 0;
|
|
mm_segment_t oldfs;
|
|
insn_size_t instruction;
|
|
int tmp;
|
|
|
|
/* Intentional ifdef */
|
|
#ifdef CONFIG_CPU_HAS_SR_RB
|
|
error_code = lookup_exception_vector();
|
|
#endif
|
|
|
|
oldfs = get_fs();
|
|
|
|
if (user_mode(regs)) {
|
|
int si_code = BUS_ADRERR;
|
|
unsigned int user_action;
|
|
|
|
local_irq_enable();
|
|
inc_unaligned_user_access();
|
|
|
|
set_fs(USER_DS);
|
|
if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
|
|
sizeof(instruction))) {
|
|
set_fs(oldfs);
|
|
goto uspace_segv;
|
|
}
|
|
set_fs(oldfs);
|
|
|
|
/* shout about userspace fixups */
|
|
unaligned_fixups_notify(current, instruction, regs);
|
|
|
|
user_action = unaligned_user_action();
|
|
if (user_action & UM_FIXUP)
|
|
goto fixup;
|
|
if (user_action & UM_SIGNAL)
|
|
goto uspace_segv;
|
|
else {
|
|
/* ignore */
|
|
regs->pc += instruction_size(instruction);
|
|
return;
|
|
}
|
|
|
|
fixup:
|
|
/* bad PC is not something we can fix */
|
|
if (regs->pc & 1) {
|
|
si_code = BUS_ADRALN;
|
|
goto uspace_segv;
|
|
}
|
|
|
|
set_fs(USER_DS);
|
|
tmp = handle_unaligned_access(instruction, regs,
|
|
&user_mem_access, 0,
|
|
address);
|
|
set_fs(oldfs);
|
|
|
|
if (tmp == 0)
|
|
return; /* sorted */
|
|
uspace_segv:
|
|
printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
|
|
"access (PC %lx PR %lx)\n", current->comm, regs->pc,
|
|
regs->pr);
|
|
|
|
force_sig_fault(SIGBUS, si_code, (void __user *)address, current);
|
|
} else {
|
|
inc_unaligned_kernel_access();
|
|
|
|
if (regs->pc & 1)
|
|
die("unaligned program counter", regs, error_code);
|
|
|
|
set_fs(KERNEL_DS);
|
|
if (copy_from_user(&instruction, (void __user *)(regs->pc),
|
|
sizeof(instruction))) {
|
|
/* Argh. Fault on the instruction itself.
|
|
This should never happen non-SMP
|
|
*/
|
|
set_fs(oldfs);
|
|
die("insn faulting in do_address_error", regs, 0);
|
|
}
|
|
|
|
unaligned_fixups_notify(current, instruction, regs);
|
|
|
|
handle_unaligned_access(instruction, regs, &user_mem_access,
|
|
0, address);
|
|
set_fs(oldfs);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SH_DSP
|
|
/*
|
|
* SH-DSP support gerg@snapgear.com.
|
|
*/
|
|
int is_dsp_inst(struct pt_regs *regs)
|
|
{
|
|
unsigned short inst = 0;
|
|
|
|
/*
|
|
* Safe guard if DSP mode is already enabled or we're lacking
|
|
* the DSP altogether.
|
|
*/
|
|
if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
|
|
return 0;
|
|
|
|
get_user(inst, ((unsigned short *) regs->pc));
|
|
|
|
inst &= 0xf000;
|
|
|
|
/* Check for any type of DSP or support instruction */
|
|
if ((inst == 0xf000) || (inst == 0x4000))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define is_dsp_inst(regs) (0)
|
|
#endif /* CONFIG_SH_DSP */
|
|
|
|
#ifdef CONFIG_CPU_SH2A
|
|
asmlinkage void do_divide_error(unsigned long r4)
|
|
{
|
|
int code;
|
|
|
|
switch (r4) {
|
|
case TRAP_DIVZERO_ERROR:
|
|
code = FPE_INTDIV;
|
|
break;
|
|
case TRAP_DIVOVF_ERROR:
|
|
code = FPE_INTOVF;
|
|
break;
|
|
default:
|
|
/* Let gcc know unhandled cases don't make it past here */
|
|
return;
|
|
}
|
|
force_sig_fault(SIGFPE, code, NULL, current);
|
|
}
|
|
#endif
|
|
|
|
asmlinkage void do_reserved_inst(void)
|
|
{
|
|
struct pt_regs *regs = current_pt_regs();
|
|
unsigned long error_code;
|
|
struct task_struct *tsk = current;
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
unsigned short inst = 0;
|
|
int err;
|
|
|
|
get_user(inst, (unsigned short*)regs->pc);
|
|
|
|
err = do_fpu_inst(inst, regs);
|
|
if (!err) {
|
|
regs->pc += instruction_size(inst);
|
|
return;
|
|
}
|
|
/* not a FPU inst. */
|
|
#endif
|
|
|
|
#ifdef CONFIG_SH_DSP
|
|
/* Check if it's a DSP instruction */
|
|
if (is_dsp_inst(regs)) {
|
|
/* Enable DSP mode, and restart instruction. */
|
|
regs->sr |= SR_DSP;
|
|
/* Save DSP mode */
|
|
tsk->thread.dsp_status.status |= SR_DSP;
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
error_code = lookup_exception_vector();
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL, tsk);
|
|
die_if_no_fixup("reserved instruction", regs, error_code);
|
|
}
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
static int emulate_branch(unsigned short inst, struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* bfs: 8fxx: PC+=d*2+4;
|
|
* bts: 8dxx: PC+=d*2+4;
|
|
* bra: axxx: PC+=D*2+4;
|
|
* bsr: bxxx: PC+=D*2+4 after PR=PC+4;
|
|
* braf:0x23: PC+=Rn*2+4;
|
|
* bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
|
|
* jmp: 4x2b: PC=Rn;
|
|
* jsr: 4x0b: PC=Rn after PR=PC+4;
|
|
* rts: 000b: PC=PR;
|
|
*/
|
|
if (((inst & 0xf000) == 0xb000) || /* bsr */
|
|
((inst & 0xf0ff) == 0x0003) || /* bsrf */
|
|
((inst & 0xf0ff) == 0x400b)) /* jsr */
|
|
regs->pr = regs->pc + 4;
|
|
|
|
if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
|
|
regs->pc += SH_PC_8BIT_OFFSET(inst);
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
|
|
regs->pc += SH_PC_12BIT_OFFSET(inst);
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
|
|
regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
|
|
regs->pc = regs->regs[(inst & 0x0f00) >> 8];
|
|
return 0;
|
|
}
|
|
|
|
if ((inst & 0xffff) == 0x000b) { /* rts */
|
|
regs->pc = regs->pr;
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
asmlinkage void do_illegal_slot_inst(void)
|
|
{
|
|
struct pt_regs *regs = current_pt_regs();
|
|
unsigned long inst;
|
|
struct task_struct *tsk = current;
|
|
|
|
if (kprobe_handle_illslot(regs->pc) == 0)
|
|
return;
|
|
|
|
#ifdef CONFIG_SH_FPU_EMU
|
|
get_user(inst, (unsigned short *)regs->pc + 1);
|
|
if (!do_fpu_inst(inst, regs)) {
|
|
get_user(inst, (unsigned short *)regs->pc);
|
|
if (!emulate_branch(inst, regs))
|
|
return;
|
|
/* fault in branch.*/
|
|
}
|
|
/* not a FPU inst. */
|
|
#endif
|
|
|
|
inst = lookup_exception_vector();
|
|
|
|
local_irq_enable();
|
|
force_sig(SIGILL, tsk);
|
|
die_if_no_fixup("illegal slot instruction", regs, inst);
|
|
}
|
|
|
|
asmlinkage void do_exception_error(void)
|
|
{
|
|
long ex;
|
|
|
|
ex = lookup_exception_vector();
|
|
die_if_kernel("exception", current_pt_regs(), ex);
|
|
}
|
|
|
|
void per_cpu_trap_init(void)
|
|
{
|
|
extern void *vbr_base;
|
|
|
|
/* NOTE: The VBR value should be at P1
|
|
(or P2, virtural "fixed" address space).
|
|
It's definitely should not in physical address. */
|
|
|
|
asm volatile("ldc %0, vbr"
|
|
: /* no output */
|
|
: "r" (&vbr_base)
|
|
: "memory");
|
|
|
|
/* disable exception blocking now when the vbr has been setup */
|
|
clear_bl_bit();
|
|
}
|
|
|
|
void *set_exception_table_vec(unsigned int vec, void *handler)
|
|
{
|
|
extern void *exception_handling_table[];
|
|
void *old_handler;
|
|
|
|
old_handler = exception_handling_table[vec];
|
|
exception_handling_table[vec] = handler;
|
|
return old_handler;
|
|
}
|
|
|
|
void __init trap_init(void)
|
|
{
|
|
set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
|
|
set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
|
|
|
|
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
|
|
defined(CONFIG_SH_FPU_EMU)
|
|
/*
|
|
* For SH-4 lacking an FPU, treat floating point instructions as
|
|
* reserved. They'll be handled in the math-emu case, or faulted on
|
|
* otherwise.
|
|
*/
|
|
set_exception_table_evt(0x800, do_reserved_inst);
|
|
set_exception_table_evt(0x820, do_illegal_slot_inst);
|
|
#elif defined(CONFIG_SH_FPU)
|
|
set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
|
|
set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_SH2
|
|
set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
|
|
#endif
|
|
#ifdef CONFIG_CPU_SH2A
|
|
set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
|
|
set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
|
|
#ifdef CONFIG_SH_FPU
|
|
set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef TRAP_UBC
|
|
set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
|
|
#endif
|
|
}
|