forked from Minki/linux
a38f98735e
Magic hex constants are a guarantee for wreckage when the defines change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
414 lines
11 KiB
C
414 lines
11 KiB
C
/*
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* apb_timer.c: Driver for Langwell APB timers
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*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* Note:
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* Langwell is the south complex of Intel Moorestown MID platform. There are
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* eight external timers in total that can be used by the operating system.
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* The timer information, such as frequency and addresses, is provided to the
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* OS via SFI tables.
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* Timer interrupts are routed via FW/HW emulated IOAPIC independently via
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* individual redirection table entries (RTE).
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* Unlike HPET, there is no master counter, therefore one of the timers are
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* used as clocksource. The overall allocation looks like:
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* - timer 0 - NR_CPUs for per cpu timer
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* - one timer for clocksource
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* - one timer for watchdog driver.
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* It is also worth notice that APB timer does not support true one-shot mode,
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* free-running mode will be used here to emulate one-shot mode.
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* APB timer can also be used as broadcast timer along with per cpu local APIC
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* timer, but by default APB timer has higher rating than local APIC timers.
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*/
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#include <linux/delay.h>
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#include <linux/dw_apb_timer.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/pm.h>
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#include <linux/sfi.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/irq.h>
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#include <asm/fixmap.h>
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#include <asm/apb_timer.h>
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#include <asm/intel-mid.h>
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#include <asm/time.h>
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#define APBT_CLOCKEVENT_RATING 110
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#define APBT_CLOCKSOURCE_RATING 250
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#define APBT_CLOCKEVENT0_NUM (0)
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#define APBT_CLOCKSOURCE_NUM (2)
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static phys_addr_t apbt_address;
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static int apb_timer_block_enabled;
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static void __iomem *apbt_virt_address;
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/*
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* Common DW APB timer info
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*/
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static unsigned long apbt_freq;
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struct apbt_dev {
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struct dw_apb_clock_event_device *timer;
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unsigned int num;
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int cpu;
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unsigned int irq;
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char name[10];
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};
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static struct dw_apb_clocksource *clocksource_apbt;
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static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
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{
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return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
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}
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static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
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#ifdef CONFIG_SMP
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static unsigned int apbt_num_timers_used;
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#endif
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static inline void apbt_set_mapping(void)
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{
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struct sfi_timer_table_entry *mtmr;
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int phy_cs_timer_id = 0;
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if (apbt_virt_address) {
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pr_debug("APBT base already mapped\n");
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return;
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}
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mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
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if (mtmr == NULL) {
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printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
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APBT_CLOCKEVENT0_NUM);
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return;
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}
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apbt_address = (phys_addr_t)mtmr->phys_addr;
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if (!apbt_address) {
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printk(KERN_WARNING "No timer base from SFI, use default\n");
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apbt_address = APBT_DEFAULT_BASE;
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}
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apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
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if (!apbt_virt_address) {
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pr_debug("Failed mapping APBT phy address at %lu\n",\
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(unsigned long)apbt_address);
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goto panic_noapbt;
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}
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apbt_freq = mtmr->freq_hz;
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sfi_free_mtmr(mtmr);
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/* Now figure out the physical timer id for clocksource device */
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mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
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if (mtmr == NULL)
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goto panic_noapbt;
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/* Now figure out the physical timer id */
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pr_debug("Use timer %d for clocksource\n",
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(int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
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phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
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APBTMRS_REG_SIZE;
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clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
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"apbt0", apbt_virt_address + phy_cs_timer_id *
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APBTMRS_REG_SIZE, apbt_freq);
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return;
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panic_noapbt:
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panic("Failed to setup APB system timer\n");
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}
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static inline void apbt_clear_mapping(void)
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{
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iounmap(apbt_virt_address);
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apbt_virt_address = NULL;
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}
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static int __init apbt_clockevent_register(void)
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{
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struct sfi_timer_table_entry *mtmr;
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struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
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mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
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if (mtmr == NULL) {
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printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
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APBT_CLOCKEVENT0_NUM);
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return -ENODEV;
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}
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adev->num = smp_processor_id();
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adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
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intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
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APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
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adev_virt_addr(adev), 0, apbt_freq);
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/* Firmware does EOI handling for us. */
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adev->timer->eoi = NULL;
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if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
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global_clock_event = &adev->timer->ced;
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printk(KERN_DEBUG "%s clockevent registered as global\n",
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global_clock_event->name);
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}
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dw_apb_clockevent_register(adev->timer);
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sfi_free_mtmr(mtmr);
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return 0;
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}
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#ifdef CONFIG_SMP
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static void apbt_setup_irq(struct apbt_dev *adev)
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{
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irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
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irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
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}
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/* Should be called with per cpu */
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void apbt_setup_secondary_clock(void)
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{
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struct apbt_dev *adev;
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int cpu;
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/* Don't register boot CPU clockevent */
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cpu = smp_processor_id();
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if (!cpu)
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return;
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adev = this_cpu_ptr(&cpu_apbt_dev);
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if (!adev->timer) {
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adev->timer = dw_apb_clockevent_init(cpu, adev->name,
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APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
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adev->irq, apbt_freq);
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adev->timer->eoi = NULL;
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} else {
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dw_apb_clockevent_resume(adev->timer);
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}
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printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
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cpu, adev->name, adev->cpu);
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apbt_setup_irq(adev);
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dw_apb_clockevent_register(adev->timer);
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return;
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}
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/*
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* this notify handler process CPU hotplug events. in case of S0i3, nonboot
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* cpus are disabled/enabled frequently, for performance reasons, we keep the
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* per cpu timer irq registered so that we do need to do free_irq/request_irq.
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*
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* TODO: it might be more reliable to directly disable percpu clockevent device
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* without the notifier chain. currently, cpu 0 may get interrupts from other
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* cpu timers during the offline process due to the ordering of notification.
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* the extra interrupt is harmless.
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*/
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static int apbt_cpuhp_notify(struct notifier_block *n,
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unsigned long action, void *hcpu)
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{
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unsigned long cpu = (unsigned long)hcpu;
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struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_DEAD:
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dw_apb_clockevent_pause(adev->timer);
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if (system_state == SYSTEM_RUNNING) {
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pr_debug("skipping APBT CPU %lu offline\n", cpu);
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} else {
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pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
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dw_apb_clockevent_stop(adev->timer);
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}
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break;
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default:
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pr_debug("APBT notified %lu, no action\n", action);
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}
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return NOTIFY_OK;
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}
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static __init int apbt_late_init(void)
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{
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if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
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!apb_timer_block_enabled)
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return 0;
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/* This notifier should be called after workqueue is ready */
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hotcpu_notifier(apbt_cpuhp_notify, -20);
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return 0;
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}
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fs_initcall(apbt_late_init);
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#else
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void apbt_setup_secondary_clock(void) {}
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#endif /* CONFIG_SMP */
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static int apbt_clocksource_register(void)
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{
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u64 start, now;
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cycle_t t1;
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/* Start the counter, use timer 2 as source, timer 0/1 for event */
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dw_apb_clocksource_start(clocksource_apbt);
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/* Verify whether apbt counter works */
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t1 = dw_apb_clocksource_read(clocksource_apbt);
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start = rdtsc();
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/*
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* We don't know the TSC frequency yet, but waiting for
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* 200000 TSC cycles is safe:
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* 4 GHz == 50us
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* 1 GHz == 200us
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*/
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do {
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rep_nop();
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now = rdtsc();
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} while ((now - start) < 200000UL);
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/* APBT is the only always on clocksource, it has to work! */
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if (t1 == dw_apb_clocksource_read(clocksource_apbt))
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panic("APBT counter not counting. APBT disabled\n");
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dw_apb_clocksource_register(clocksource_apbt);
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return 0;
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}
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/*
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* Early setup the APBT timer, only use timer 0 for booting then switch to
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* per CPU timer if possible.
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* returns 1 if per cpu apbt is setup
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* returns 0 if no per cpu apbt is chosen
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* panic if set up failed, this is the only platform timer on Moorestown.
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*/
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void __init apbt_time_init(void)
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{
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#ifdef CONFIG_SMP
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int i;
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struct sfi_timer_table_entry *p_mtmr;
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struct apbt_dev *adev;
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#endif
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if (apb_timer_block_enabled)
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return;
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apbt_set_mapping();
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if (!apbt_virt_address)
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goto out_noapbt;
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/*
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* Read the frequency and check for a sane value, for ESL model
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* we extend the possible clock range to allow time scaling.
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*/
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if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
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pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
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goto out_noapbt;
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}
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if (apbt_clocksource_register()) {
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pr_debug("APBT has failed to register clocksource\n");
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goto out_noapbt;
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}
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if (!apbt_clockevent_register())
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apb_timer_block_enabled = 1;
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else {
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pr_debug("APBT has failed to register clockevent\n");
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goto out_noapbt;
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}
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#ifdef CONFIG_SMP
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/* kernel cmdline disable apb timer, so we will use lapic timers */
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if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
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printk(KERN_INFO "apbt: disabled per cpu timer\n");
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return;
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}
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pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
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if (num_possible_cpus() <= sfi_mtimer_num)
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apbt_num_timers_used = num_possible_cpus();
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else
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apbt_num_timers_used = 1;
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pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
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/* here we set up per CPU timer data structure */
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for (i = 0; i < apbt_num_timers_used; i++) {
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adev = &per_cpu(cpu_apbt_dev, i);
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adev->num = i;
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adev->cpu = i;
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p_mtmr = sfi_get_mtmr(i);
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if (p_mtmr)
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adev->irq = p_mtmr->irq;
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else
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printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
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snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
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}
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#endif
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return;
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out_noapbt:
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apbt_clear_mapping();
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apb_timer_block_enabled = 0;
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panic("failed to enable APB timer\n");
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}
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/* called before apb_timer_enable, use early map */
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unsigned long apbt_quick_calibrate(void)
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{
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int i, scale;
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u64 old, new;
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cycle_t t1, t2;
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unsigned long khz = 0;
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u32 loop, shift;
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apbt_set_mapping();
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dw_apb_clocksource_start(clocksource_apbt);
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/* check if the timer can count down, otherwise return */
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old = dw_apb_clocksource_read(clocksource_apbt);
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i = 10000;
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while (--i) {
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if (old != dw_apb_clocksource_read(clocksource_apbt))
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break;
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}
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if (!i)
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goto failed;
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/* count 16 ms */
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loop = (apbt_freq / 1000) << 4;
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/* restart the timer to ensure it won't get to 0 in the calibration */
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dw_apb_clocksource_start(clocksource_apbt);
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old = dw_apb_clocksource_read(clocksource_apbt);
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old += loop;
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t1 = rdtsc();
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do {
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new = dw_apb_clocksource_read(clocksource_apbt);
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} while (new < old);
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t2 = rdtsc();
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shift = 5;
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if (unlikely(loop >> shift == 0)) {
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printk(KERN_INFO
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"APBT TSC calibration failed, not enough resolution\n");
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return 0;
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}
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scale = (int)div_u64((t2 - t1), loop >> shift);
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khz = (scale * (apbt_freq / 1000)) >> shift;
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printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
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return khz;
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failed:
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return 0;
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}
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