forked from Minki/linux
2daab50e17
Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> [Laurentiu.Tudor@freescale.com: rebased on latest kernel, use define instead of hardcoded value, moved code in own function] Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Acked-by: Scott Wood <scotttwood@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
124 lines
2.7 KiB
C
124 lines
2.7 KiB
C
/*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License, version 2, as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* Copyright IBM Corp. 2008
|
|
*
|
|
* Authors: Hollis Blanchard <hollisb@us.ibm.com>
|
|
*/
|
|
|
|
#ifndef __ASM_PPC_DISASSEMBLE_H__
|
|
#define __ASM_PPC_DISASSEMBLE_H__
|
|
|
|
#include <linux/types.h>
|
|
|
|
static inline unsigned int get_op(u32 inst)
|
|
{
|
|
return inst >> 26;
|
|
}
|
|
|
|
static inline unsigned int get_xop(u32 inst)
|
|
{
|
|
return (inst >> 1) & 0x3ff;
|
|
}
|
|
|
|
static inline unsigned int get_sprn(u32 inst)
|
|
{
|
|
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
|
|
}
|
|
|
|
static inline unsigned int get_dcrn(u32 inst)
|
|
{
|
|
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
|
|
}
|
|
|
|
static inline unsigned int get_tmrn(u32 inst)
|
|
{
|
|
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
|
|
}
|
|
|
|
static inline unsigned int get_rt(u32 inst)
|
|
{
|
|
return (inst >> 21) & 0x1f;
|
|
}
|
|
|
|
static inline unsigned int get_rs(u32 inst)
|
|
{
|
|
return (inst >> 21) & 0x1f;
|
|
}
|
|
|
|
static inline unsigned int get_ra(u32 inst)
|
|
{
|
|
return (inst >> 16) & 0x1f;
|
|
}
|
|
|
|
static inline unsigned int get_rb(u32 inst)
|
|
{
|
|
return (inst >> 11) & 0x1f;
|
|
}
|
|
|
|
static inline unsigned int get_rc(u32 inst)
|
|
{
|
|
return inst & 0x1;
|
|
}
|
|
|
|
static inline unsigned int get_ws(u32 inst)
|
|
{
|
|
return (inst >> 11) & 0x1f;
|
|
}
|
|
|
|
static inline unsigned int get_d(u32 inst)
|
|
{
|
|
return inst & 0xffff;
|
|
}
|
|
|
|
static inline unsigned int get_oc(u32 inst)
|
|
{
|
|
return (inst >> 11) & 0x7fff;
|
|
}
|
|
|
|
#define IS_XFORM(inst) (get_op(inst) == 31)
|
|
#define IS_DSFORM(inst) (get_op(inst) >= 56)
|
|
|
|
/*
|
|
* Create a DSISR value from the instruction
|
|
*/
|
|
static inline unsigned make_dsisr(unsigned instr)
|
|
{
|
|
unsigned dsisr;
|
|
|
|
|
|
/* bits 6:15 --> 22:31 */
|
|
dsisr = (instr & 0x03ff0000) >> 16;
|
|
|
|
if (IS_XFORM(instr)) {
|
|
/* bits 29:30 --> 15:16 */
|
|
dsisr |= (instr & 0x00000006) << 14;
|
|
/* bit 25 --> 17 */
|
|
dsisr |= (instr & 0x00000040) << 8;
|
|
/* bits 21:24 --> 18:21 */
|
|
dsisr |= (instr & 0x00000780) << 3;
|
|
} else {
|
|
/* bit 5 --> 17 */
|
|
dsisr |= (instr & 0x04000000) >> 12;
|
|
/* bits 1: 4 --> 18:21 */
|
|
dsisr |= (instr & 0x78000000) >> 17;
|
|
/* bits 30:31 --> 12:13 */
|
|
if (IS_DSFORM(instr))
|
|
dsisr |= (instr & 0x00000003) << 18;
|
|
}
|
|
|
|
return dsisr;
|
|
}
|
|
#endif /* __ASM_PPC_DISASSEMBLE_H__ */
|