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Fixes: 9b86b1b41e ("docs: perf: Add new description on HiSilicon uncore PMU v2")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Link: https://lore.kernel.org/r/1617021121-31450-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
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======================================================
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HiSilicon SoC uncore Performance Monitoring Unit (PMU)
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======================================================
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The HiSilicon SoC chip includes various independent system device PMUs
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such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
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independent and have hardware logic to gather statistics and performance
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information.
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The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
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(CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
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called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
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two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
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HiSilicon SoC uncore PMU driver
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-------------------------------
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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see:
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/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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The "perf list" command shall list the available events from sysfs.
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Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
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where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
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module.
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e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
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SCCL ID #3.
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e.g. hisi_sccl1_hha0/rx_operations is RX_OPERATIONS event of HHA index #0 in
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SCCL ID #1.
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The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
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ID used to count the uncore PMU event.
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Example usage of perf::
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$# perf list
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hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
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------------------------------------------
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$# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
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For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
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as PMU v1, but some new functions are added to the hardware.
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(a) L3C PMU supports filtering by core/thread within the cluster which can be
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specified as a bitmap::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
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This will only count the operations from core/thread 0 and 1 in this cluster.
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(b) Tracetag allow the user to chose to count only read, write or atomic
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operations via the tt_req parameeter in perf. The default value counts all
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operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101
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represents write operations, 3'b110 represents atomic store operations and
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3'b111 represents atomic non-store operations, other values are reserved::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
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This will only count the read operations in this cluster.
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(c) Datasrc allows the user to check where the data comes from. It is 5 bits.
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Some important codes are as follows:
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5'b00001: comes from L3C in this die;
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5'b01000: comes from L3C in the cross-die;
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5'b01001: comes from L3C which is in another socket;
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5'b01110: comes from the local DDR;
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5'b01111: comes from the cross-die DDR;
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5'b10000: comes from cross-socket DDR;
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etc, it is mainly helpful to find that the data source is nearest from the CPU
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cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
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configured in perf command::
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$# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
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hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xF/ sleep 5
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(d)Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die
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contains several Compute Clusters (CCLs). The I/O dies are called Super I/O
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clusters (SICL) containing multiple I/O clusters (ICLs). Each CCL/ICL in the
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SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
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CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
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5'b00000: I/O_MGMT_ICL;
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5'b00001: Network_ICL;
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5'b00011: HAC_ICL;
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5'b10000: PCIe_ICL;
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Users could configure IDs to count data come from specific CCL/ICL, by setting
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srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
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tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
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check the bit when matching against the srcid_cmd/tgtid_cmd.
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If all of these options are disabled, it can works by the default value that
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doesn't distinguish the filter condition and ID information and will return
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the total counter values in the PMU counters.
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The current driver does not support sampling. So "perf record" is unsupported.
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Also attach to a task is unsupported as the events are all uncore.
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Note: Please contact the maintainer for a complete list of events supported for
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the PMU devices in the SoC and its information if needed.
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