..
clk-div6.c
clk: renesas: div6: Combine clock-private and parent array allocation
2019-06-20 11:36:29 +02:00
clk-div6.h
We have two changes to the core framework this time around. The first being a
2017-11-17 20:04:24 -08:00
clk-emev2.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-mstp.c
clk: renesas: mstp: Delete unnecessary kfree() in cpg_mstp_clocks_init()
2019-10-01 09:50:28 +02:00
clk-r8a73a4.c
clk: Remove io.h from clk-provider.h
2019-05-15 13:21:37 -07:00
clk-r8a7740.c
clk: Remove io.h from clk-provider.h
2019-05-15 13:21:37 -07:00
clk-r8a7778.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-r8a7779.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-rz.c
remove ioremap_nocache and devm_ioremap_nocache
2020-01-06 09:45:59 +01:00
clk-sh73a0.c
clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
2020-12-10 08:34:01 +01:00
Kconfig
clk: renesas: rcar-gen3: Update description for RZ/G2
2020-09-17 15:32:25 +02:00
Makefile
clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-17 15:32:25 +02:00
r7s9210-cpg-mssr.c
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
clk: renesas: r8a774a1: Add RPC clocks
2020-12-10 08:34:01 +01:00
r8a774b1-cpg-mssr.c
clk: renesas: r8a774b1: Add RPC clocks
2020-12-10 08:34:01 +01:00
r8a774c0-cpg-mssr.c
clk: renesas: r8a774c0: Add RPC clocks
2020-12-10 08:34:01 +01:00
r8a774e1-cpg-mssr.c
clk: renesas: cpg-mssr: Add r8a774e1 support
2020-07-13 10:36:33 +02:00
r8a779a0-cpg-mssr.c
clk: renesas: r8a779a0: Fix R and OSC clocks
2020-12-10 08:34:01 +01:00
r8a7742-cpg-mssr.c
clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a7796-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77470-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77970-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77980-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77990-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r8a77995-cpg-mssr.c
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
2020-06-22 16:53:49 +02:00
r9a06g032-clocks.c
clk: renesas: r9a06g032: Fix some typo in comments
2020-04-14 09:22:16 +02:00
rcar-gen2-cpg.c
clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
2019-10-21 09:53:43 +02:00
rcar-gen2-cpg.h
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c
clk: renesas: r8a774c0: Add RPC clocks
2020-12-10 08:34:01 +01:00
rcar-gen3-cpg.h
clk: renesas: r8a774c0: Add RPC clocks
2020-12-10 08:34:01 +01:00
rcar-usb2-clock-sel.c
clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
2020-12-10 08:34:01 +01:00
renesas-cpg-mssr.c
clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
2020-12-10 08:34:01 +01:00
renesas-cpg-mssr.h
clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-17 15:32:25 +02:00
fd0d8ed7c1