forked from Minki/linux
548 lines
16 KiB
C
548 lines
16 KiB
C
/*
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* Copyright 2005 Stephane Marchesin.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NOUVEAU_DRV_H__
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#define __NOUVEAU_DRV_H__
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#define DRIVER_AUTHOR "Stephane Marchesin"
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#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
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#define DRIVER_NAME "nouveau"
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#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
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#define DRIVER_DATE "20120316"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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#define NOUVEAU_FAMILY 0x0000FFFF
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#define NOUVEAU_FLAGS 0xFFFF0000
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#include "ttm/ttm_bo_api.h"
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#include "ttm/ttm_bo_driver.h"
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#include "ttm/ttm_placement.h"
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#include "ttm/ttm_memory.h"
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#include "ttm/ttm_module.h"
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#define XXX_THIS_IS_A_HACK
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#include <subdev/vm.h>
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#include <subdev/fb.h>
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#include <core/gpuobj.h>
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enum blah {
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NV_MEM_TYPE_UNKNOWN = 0,
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NV_MEM_TYPE_STOLEN,
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NV_MEM_TYPE_SGRAM,
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NV_MEM_TYPE_SDRAM,
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NV_MEM_TYPE_DDR1,
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NV_MEM_TYPE_DDR2,
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NV_MEM_TYPE_DDR3,
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NV_MEM_TYPE_GDDR2,
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NV_MEM_TYPE_GDDR3,
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NV_MEM_TYPE_GDDR4,
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NV_MEM_TYPE_GDDR5
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};
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#include <nouveau_drm.h>
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#include "nouveau_reg.h"
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#include <nouveau_bios.h>
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#include <subdev/bios/pll.h>
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#include "nouveau_compat.h"
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#define nouveau_gpuobj_new(d,c,s,a,f,o) \
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_nouveau_gpuobj_new((d), NULL, (s), (a), (f), (o))
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#define nouveau_vm_new(d,o,l,m,v) \
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_nouveau_vm_new((d), (o), (l), (m), (v))
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#define nv50_vm_flush_engine(d,e) \
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_nv50_vm_flush_engine((d), (e))
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#include "nouveau_bo.h"
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#include "nouveau_gem.h"
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struct nouveau_page_flip_state {
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struct list_head head;
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struct drm_pending_vblank_event *event;
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int crtc, bpp, pitch, x, y;
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uint64_t offset;
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};
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struct nouveau_display_engine {
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void *priv;
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int (*early_init)(struct drm_device *);
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void (*late_takedown)(struct drm_device *);
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int (*create)(struct drm_device *);
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void (*destroy)(struct drm_device *);
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int (*init)(struct drm_device *);
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void (*fini)(struct drm_device *);
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struct drm_property *dithering_mode;
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struct drm_property *dithering_depth;
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struct drm_property *underscan_property;
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struct drm_property *underscan_hborder_property;
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struct drm_property *underscan_vborder_property;
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/* not really hue and saturation: */
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struct drm_property *vibrant_hue_property;
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struct drm_property *color_vibrance_property;
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};
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struct nouveau_pm_voltage_level {
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u32 voltage; /* microvolts */
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u8 vid;
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};
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struct nouveau_pm_voltage {
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bool supported;
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u8 version;
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u8 vid_mask;
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struct nouveau_pm_voltage_level *level;
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int nr_level;
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};
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/* Exclusive upper limits */
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#define NV_MEM_CL_DDR2_MAX 8
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#define NV_MEM_WR_DDR2_MAX 9
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#define NV_MEM_CL_DDR3_MAX 17
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#define NV_MEM_WR_DDR3_MAX 17
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#define NV_MEM_CL_GDDR3_MAX 16
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#define NV_MEM_WR_GDDR3_MAX 18
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#define NV_MEM_CL_GDDR5_MAX 21
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#define NV_MEM_WR_GDDR5_MAX 20
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struct nouveau_pm_memtiming {
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int id;
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u32 reg[9];
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u32 mr[4];
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u8 tCWL;
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u8 odt;
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u8 drive_strength;
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};
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struct nouveau_pm_tbl_header {
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u8 version;
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u8 header_len;
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u8 entry_cnt;
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u8 entry_len;
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};
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struct nouveau_pm_tbl_entry {
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u8 tWR;
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u8 tWTR;
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u8 tCL;
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u8 tRC;
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u8 empty_4;
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u8 tRFC; /* Byte 5 */
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u8 empty_6;
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u8 tRAS; /* Byte 7 */
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u8 empty_8;
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u8 tRP; /* Byte 9 */
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u8 tRCDRD;
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u8 tRCDWR;
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u8 tRRD;
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u8 tUNK_13;
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u8 RAM_FT1; /* 14, a bitmask of random RAM features */
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u8 empty_15;
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u8 tUNK_16;
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u8 empty_17;
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u8 tUNK_18;
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u8 tCWL;
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u8 tUNK_20, tUNK_21;
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};
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struct nouveau_pm_profile;
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struct nouveau_pm_profile_func {
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void (*destroy)(struct nouveau_pm_profile *);
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void (*init)(struct nouveau_pm_profile *);
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void (*fini)(struct nouveau_pm_profile *);
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struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
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};
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struct nouveau_pm_profile {
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const struct nouveau_pm_profile_func *func;
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struct list_head head;
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char name[8];
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};
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#define NOUVEAU_PM_MAX_LEVEL 8
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struct nouveau_pm_level {
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struct nouveau_pm_profile profile;
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struct device_attribute dev_attr;
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char name[32];
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int id;
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struct nouveau_pm_memtiming timing;
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u32 memory;
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u16 memscript;
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u32 core;
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u32 shader;
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u32 rop;
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u32 copy;
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u32 daemon;
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u32 vdec;
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u32 dom6;
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u32 unka0; /* nva3:nvc0 */
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u32 hub01; /* nvc0- */
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u32 hub06; /* nvc0- */
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u32 hub07; /* nvc0- */
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u32 volt_min; /* microvolts */
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u32 volt_max;
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u8 fanspeed;
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};
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struct nouveau_pm_temp_sensor_constants {
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u16 offset_constant;
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s16 offset_mult;
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s16 offset_div;
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s16 slope_mult;
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s16 slope_div;
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};
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struct nouveau_pm_threshold_temp {
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s16 critical;
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s16 down_clock;
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s16 fan_boost;
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};
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struct nouveau_pm_fan {
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u32 percent;
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u32 min_duty;
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u32 max_duty;
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u32 pwm_freq;
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u32 pwm_divisor;
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};
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struct nouveau_pm_engine {
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struct nouveau_pm_voltage voltage;
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struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
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int nr_perflvl;
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struct nouveau_pm_temp_sensor_constants sensor_constants;
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struct nouveau_pm_threshold_temp threshold_temp;
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struct nouveau_pm_fan fan;
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struct nouveau_pm_profile *profile_ac;
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struct nouveau_pm_profile *profile_dc;
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struct nouveau_pm_profile *profile;
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struct list_head profiles;
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struct nouveau_pm_level boot;
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struct nouveau_pm_level *cur;
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struct device *hwmon;
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struct notifier_block acpi_nb;
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int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
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void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
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int (*clocks_set)(struct drm_device *, void *);
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int (*voltage_get)(struct drm_device *);
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int (*voltage_set)(struct drm_device *, int voltage);
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int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
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int (*pwm_set)(struct drm_device *, int line, u32, u32);
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int (*temp_get)(struct drm_device *);
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};
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struct nouveau_engine {
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struct nouveau_display_engine display;
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struct nouveau_pm_engine pm;
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};
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enum nouveau_card_type {
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NV_04 = 0x04,
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NV_10 = 0x10,
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NV_20 = 0x20,
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NV_30 = 0x30,
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NV_40 = 0x40,
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NV_50 = 0x50,
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NV_C0 = 0xc0,
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NV_D0 = 0xd0,
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NV_E0 = 0xe0,
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};
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struct drm_nouveau_private {
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struct drm_device *dev;
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void *newpriv;
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/* the card type, takes NV_* as values */
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enum nouveau_card_type card_type;
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/* exact chipset, derived from NV_PMC_BOOT_0 */
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int chipset;
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u32 crystal;
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/* interrupt handling */
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void (*irq_handler[32])(struct drm_device *);
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bool msi_enabled;
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struct nouveau_engine engine;
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/* For PFIFO and PGRAPH. */
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spinlock_t context_switch_lock;
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struct nvbios vbios;
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u8 *mxms;
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struct backlight_device *backlight;
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};
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static inline struct drm_nouveau_private *
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nouveau_private(struct drm_device *dev)
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{
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return dev->dev_private;
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}
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/* nouveau_drv.c */
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extern int nouveau_modeset;
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extern int nouveau_duallink;
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extern int nouveau_uscript_lvds;
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extern int nouveau_uscript_tmds;
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extern int nouveau_vram_pushbuf;
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extern int nouveau_vram_notify;
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extern char *nouveau_vram_type;
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extern int nouveau_fbpercrtc;
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extern int nouveau_tv_disable;
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extern char *nouveau_tv_norm;
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extern int nouveau_ignorelid;
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extern int nouveau_force_post;
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extern int nouveau_override_conntype;
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extern char *nouveau_perflvl;
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extern int nouveau_perflvl_wr;
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extern int nouveau_msi;
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extern int nouveau_ctxfw;
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extern int nouveau_mxmdcb;
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extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
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extern int nouveau_pci_resume(struct pci_dev *pdev);
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/* nouveau_state.c */
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extern int nouveau_load(struct drm_device *, unsigned long flags);
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extern int nouveau_firstopen(struct drm_device *);
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extern void nouveau_lastclose(struct drm_device *);
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extern int nouveau_unload(struct drm_device *);
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extern int nouveau_card_init(struct drm_device *);
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/* nouveau_mem.c */
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extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
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struct nouveau_pm_memtiming *);
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extern void nouveau_mem_timing_read(struct drm_device *,
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struct nouveau_pm_memtiming *);
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/* nouveau_irq.c */
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extern int nouveau_irq_init(struct drm_device *);
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extern void nouveau_irq_fini(struct drm_device *);
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extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
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extern void nouveau_irq_register(struct drm_device *, int status_bit,
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void (*)(struct drm_device *));
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extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
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extern void nouveau_irq_preinstall(struct drm_device *);
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extern int nouveau_irq_postinstall(struct drm_device *);
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extern void nouveau_irq_uninstall(struct drm_device *);
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/* nouveau_backlight.c */
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#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
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extern int nouveau_backlight_init(struct drm_device *);
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extern void nouveau_backlight_exit(struct drm_device *);
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#else
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static inline int nouveau_backlight_init(struct drm_device *dev)
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{
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return 0;
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}
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static inline void nouveau_backlight_exit(struct drm_device *dev) { }
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#endif
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/* nouveau_bios.c */
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extern int nouveau_bios_init(struct drm_device *);
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extern void nouveau_bios_takedown(struct drm_device *dev);
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extern int nouveau_run_vbios_init(struct drm_device *);
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extern struct dcb_connector_table_entry *
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nouveau_bios_connector_entry(struct drm_device *, int index);
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extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
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struct dcb_output *, int crtc);
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extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
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extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
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extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
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bool *dl, bool *if_is_24bit);
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extern int run_tmds_table(struct drm_device *, struct dcb_output *,
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int head, int pxclk);
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extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
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enum LVDS_script, int pxclk);
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bool bios_encoder_match(struct dcb_output *, u32 hash);
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/* nouveau_ttm.c */
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int nouveau_ttm_global_init(struct drm_nouveau_private *);
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void nouveau_ttm_global_release(struct drm_nouveau_private *);
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int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
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/* nouveau_hdmi.c */
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void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
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/* nvd0_display.c */
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extern int nvd0_display_create(struct drm_device *);
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extern void nvd0_display_destroy(struct drm_device *);
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extern int nvd0_display_init(struct drm_device *);
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extern void nvd0_display_fini(struct drm_device *);
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struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
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void nvd0_display_flip_stop(struct drm_crtc *);
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int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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struct nouveau_channel *, u32 swap_interval);
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/* nouveau_display.c */
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int nouveau_display_create(struct drm_device *dev);
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void nouveau_display_destroy(struct drm_device *dev);
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int nouveau_display_init(struct drm_device *dev);
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void nouveau_display_fini(struct drm_device *dev);
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int nouveau_vblank_enable(struct drm_device *dev, int crtc);
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void nouveau_vblank_disable(struct drm_device *dev, int crtc);
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int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event);
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int nouveau_finish_page_flip(struct nouveau_channel *,
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struct nouveau_page_flip_state *);
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int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
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struct drm_mode_create_dumb *args);
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int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
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uint32_t handle, uint64_t *offset);
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int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
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uint32_t handle);
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#ifndef ioread32_native
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#ifdef __BIG_ENDIAN
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#define ioread16_native ioread16be
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#define iowrite16_native iowrite16be
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#define ioread32_native ioread32be
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#define iowrite32_native iowrite32be
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#else /* def __BIG_ENDIAN */
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#define ioread16_native ioread16
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#define iowrite16_native iowrite16
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#define ioread32_native ioread32
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#define iowrite32_native iowrite32
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#endif /* def __BIG_ENDIAN else */
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#endif /* !ioread32_native */
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/* register access */
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#define nv_rd08 _nv_rd08
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#define nv_wr08 _nv_wr08
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#define nv_rd32 _nv_rd32
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#define nv_wr32 _nv_wr32
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#define nv_mask _nv_mask
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#define nv_wait(dev, reg, mask, val) \
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nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
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#define nv_wait_ne(dev, reg, mask, val) \
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nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
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#define nv_wait_cb(dev, func, data) \
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nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
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/*
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* Logging
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* Argument d is (struct drm_device *).
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*/
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#define NV_PRINTK(level, d, fmt, arg...) \
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printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
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pci_name(d->pdev), ##arg)
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#ifndef NV_DEBUG_NOTRACE
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#define NV_DEBUG(d, fmt, arg...) do { \
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if (drm_debug & DRM_UT_DRIVER) { \
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NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
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__LINE__, ##arg); \
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} \
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} while (0)
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#define NV_DEBUG_KMS(d, fmt, arg...) do { \
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if (drm_debug & DRM_UT_KMS) { \
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NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
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__LINE__, ##arg); \
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} \
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} while (0)
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#else
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#define NV_DEBUG(d, fmt, arg...) do { \
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if (drm_debug & DRM_UT_DRIVER) \
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NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
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} while (0)
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#define NV_DEBUG_KMS(d, fmt, arg...) do { \
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if (drm_debug & DRM_UT_KMS) \
|
|
NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
|
|
} while (0)
|
|
#endif
|
|
#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
|
|
#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
|
|
#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
|
|
#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
|
|
#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
|
|
#define NV_WARNONCE(d, fmt, arg...) do { \
|
|
static int _warned = 0; \
|
|
if (!_warned) { \
|
|
NV_WARN(d, fmt, ##arg); \
|
|
_warned = 1; \
|
|
} \
|
|
} while(0)
|
|
|
|
static inline bool
|
|
nv_two_heads(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
const int impl = dev->pci_device & 0x0ff0;
|
|
|
|
if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
|
|
impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static inline bool
|
|
nv_gf4_disp_arch(struct drm_device *dev)
|
|
{
|
|
return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
|
|
}
|
|
|
|
static inline bool
|
|
nv_two_reg_pll(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
const int impl = dev->pci_device & 0x0ff0;
|
|
|
|
if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static inline bool
|
|
nv_match_device(struct drm_device *dev, unsigned device,
|
|
unsigned sub_vendor, unsigned sub_device)
|
|
{
|
|
return dev->pdev->device == device &&
|
|
dev->pdev->subsystem_vendor == sub_vendor &&
|
|
dev->pdev->subsystem_device == sub_device;
|
|
}
|
|
|
|
#endif /* __NOUVEAU_DRV_H__ */
|