105ae504a3
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
39 lines
1.3 KiB
Plaintext
39 lines
1.3 KiB
Plaintext
DT bindings for the Renesas R-Car and RZ/G Reset Controllers
|
|
|
|
The R-Car and RZ/G Reset Controllers provide reset control, and implement the
|
|
following functions:
|
|
- Latching of the levels on mode pins when PRESET# is negated,
|
|
- Mode monitoring register,
|
|
- Reset control of peripheral devices (on R-Car Gen1),
|
|
- Watchdog timer (on R-Car Gen1),
|
|
- Register-based reset control and boot address registers for the various CPU
|
|
cores (on R-Car Gen2 and Gen3, and on RZ/G).
|
|
|
|
|
|
Required properties:
|
|
- compatible: Should be
|
|
- "renesas,<soctype>-reset-wdt" for R-Car Gen1,
|
|
- "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G
|
|
Examples with soctypes are:
|
|
- "renesas,r8a7743-rst" (RZ/G1M)
|
|
- "renesas,r8a7745-rst" (RZ/G1E)
|
|
- "renesas,r8a7778-reset-wdt" (R-Car M1A)
|
|
- "renesas,r8a7779-reset-wdt" (R-Car H1)
|
|
- "renesas,r8a7790-rst" (R-Car H2)
|
|
- "renesas,r8a7791-rst" (R-Car M2-W)
|
|
- "renesas,r8a7792-rst" (R-Car V2H
|
|
- "renesas,r8a7793-rst" (R-Car M2-N)
|
|
- "renesas,r8a7794-rst" (R-Car E2)
|
|
- "renesas,r8a7795-rst" (R-Car H3)
|
|
- "renesas,r8a7796-rst" (R-Car M3-W)
|
|
- "renesas,r8a77995-rst" (R-Car D3)
|
|
- reg: Address start and address range for the device.
|
|
|
|
|
|
Example:
|
|
|
|
rst: reset-controller@e6160000 {
|
|
compatible = "renesas,r8a7795-rst";
|
|
reg = <0 0xe6160000 0 0x0200>;
|
|
};
|