forked from Minki/linux
26501a703d
We want to set bits 1 & 2 on easy programming byte 4, not extended byte 4. Thanks to David Wong for pointing this out. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Cc: David Wong <davidtlwong@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
773 lines
18 KiB
C
773 lines
18 KiB
C
/*
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tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
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Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/delay.h>
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#include <linux/videodev2.h>
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#include "tda18271.h"
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#include "tda18271-priv.h"
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int tda18271_debug;
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module_param_named(debug, tda18271_debug, int, 0644);
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MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
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/*---------------------------------------------------------------------*/
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enum tda18271_mode {
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TDA18271_ANALOG,
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TDA18271_DIGITAL,
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};
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struct tda18271_priv {
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u8 i2c_addr;
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struct i2c_adapter *i2c_adap;
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unsigned char tda18271_regs[TDA18271_NUM_REGS];
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enum tda18271_mode mode;
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enum tda18271_i2c_gate gate;
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u32 frequency;
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u32 bandwidth;
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};
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static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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enum tda18271_i2c_gate gate;
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int ret = 0;
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switch (priv->gate) {
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case TDA18271_GATE_DIGITAL:
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case TDA18271_GATE_ANALOG:
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gate = priv->gate;
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break;
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case TDA18271_GATE_AUTO:
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default:
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switch (priv->mode) {
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case TDA18271_DIGITAL:
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gate = TDA18271_GATE_DIGITAL;
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break;
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case TDA18271_ANALOG:
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default:
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gate = TDA18271_GATE_ANALOG;
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break;
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}
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}
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switch (gate) {
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case TDA18271_GATE_ANALOG:
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if (fe->ops.analog_ops.i2c_gate_ctrl)
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ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
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break;
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case TDA18271_GATE_DIGITAL:
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if (fe->ops.i2c_gate_ctrl)
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ret = fe->ops.i2c_gate_ctrl(fe, enable);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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};
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/*---------------------------------------------------------------------*/
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static void tda18271_dump_regs(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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dbg_reg("=== TDA18271 REG DUMP ===\n");
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dbg_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
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dbg_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
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dbg_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
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dbg_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
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dbg_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
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dbg_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
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dbg_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
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dbg_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
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dbg_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
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dbg_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
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dbg_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
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dbg_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
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dbg_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
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dbg_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
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dbg_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
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dbg_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
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}
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static void tda18271_read_regs(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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unsigned char buf = 0x00;
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int ret;
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struct i2c_msg msg[] = {
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{ .addr = priv->i2c_addr, .flags = 0,
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.buf = &buf, .len = 1 },
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{ .addr = priv->i2c_addr, .flags = I2C_M_RD,
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.buf = regs, .len = 16 }
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};
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tda18271_i2c_gate_ctrl(fe, 1);
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/* read all registers */
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ret = i2c_transfer(priv->i2c_adap, msg, 2);
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tda18271_i2c_gate_ctrl(fe, 0);
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if (ret != 2)
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printk("ERROR: %s: i2c_transfer returned: %d\n",
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__FUNCTION__, ret);
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if (tda18271_debug & DBG_REG)
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tda18271_dump_regs(fe);
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}
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static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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unsigned char buf[TDA18271_NUM_REGS+1];
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struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
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.buf = buf, .len = len+1 };
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int i, ret;
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BUG_ON((len == 0) || (idx+len > sizeof(buf)));
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buf[0] = idx;
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for (i = 1; i <= len; i++) {
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buf[i] = regs[idx-1+i];
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}
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tda18271_i2c_gate_ctrl(fe, 1);
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/* write registers */
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ret = i2c_transfer(priv->i2c_adap, &msg, 1);
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tda18271_i2c_gate_ctrl(fe, 0);
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if (ret != 1)
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printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
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__FUNCTION__, ret);
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}
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/*---------------------------------------------------------------------*/
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static int tda18271_init_regs(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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printk(KERN_INFO "tda18271: initializing registers\n");
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/* initialize registers */
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regs[R_ID] = 0x83;
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regs[R_TM] = 0x08;
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regs[R_PL] = 0x80;
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regs[R_EP1] = 0xc6;
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regs[R_EP2] = 0xdf;
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regs[R_EP3] = 0x16;
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regs[R_EP4] = 0x60;
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regs[R_EP5] = 0x80;
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regs[R_CPD] = 0x80;
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regs[R_CD1] = 0x00;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0x00;
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regs[R_MD1] = 0x00;
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regs[R_MD2] = 0x00;
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regs[R_MD3] = 0x00;
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regs[R_EB1] = 0xff;
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regs[R_EB2] = 0x01;
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regs[R_EB3] = 0x84;
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regs[R_EB4] = 0x41;
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regs[R_EB5] = 0x01;
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regs[R_EB6] = 0x84;
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regs[R_EB7] = 0x40;
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regs[R_EB8] = 0x07;
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regs[R_EB9] = 0x00;
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regs[R_EB10] = 0x00;
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regs[R_EB11] = 0x96;
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regs[R_EB12] = 0x0f;
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regs[R_EB13] = 0xc1;
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regs[R_EB14] = 0x00;
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regs[R_EB15] = 0x8f;
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regs[R_EB16] = 0x00;
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regs[R_EB17] = 0x00;
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regs[R_EB18] = 0x00;
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regs[R_EB19] = 0x00;
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regs[R_EB20] = 0x20;
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regs[R_EB21] = 0x33;
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regs[R_EB22] = 0x48;
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regs[R_EB23] = 0xb0;
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tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
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/* setup AGC1 & AGC2 */
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regs[R_EB17] = 0x00;
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tda18271_write_regs(fe, R_EB17, 1);
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regs[R_EB17] = 0x03;
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tda18271_write_regs(fe, R_EB17, 1);
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regs[R_EB17] = 0x43;
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tda18271_write_regs(fe, R_EB17, 1);
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regs[R_EB17] = 0x4c;
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tda18271_write_regs(fe, R_EB17, 1);
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regs[R_EB20] = 0xa0;
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tda18271_write_regs(fe, R_EB20, 1);
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regs[R_EB20] = 0xa7;
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tda18271_write_regs(fe, R_EB20, 1);
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regs[R_EB20] = 0xe7;
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tda18271_write_regs(fe, R_EB20, 1);
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regs[R_EB20] = 0xec;
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tda18271_write_regs(fe, R_EB20, 1);
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/* image rejection calibration */
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/* low-band */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x81;
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regs[R_CPD] = 0xcc;
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regs[R_CD1] = 0x6c;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0xcd;
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regs[R_MD1] = 0x77;
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regs[R_MD2] = 0x08;
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regs[R_MD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 11);
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msleep(5); /* pll locking */
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regs[R_EP1] = 0xc6;
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tda18271_write_regs(fe, R_EP1, 1);
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msleep(5); /* wanted low measurement */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x85;
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regs[R_CPD] = 0xcb;
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regs[R_CD1] = 0x66;
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regs[R_CD2] = 0x70;
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regs[R_CD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 7);
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msleep(5); /* pll locking */
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regs[R_EP2] = 0xdf;
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tda18271_write_regs(fe, R_EP2, 1);
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msleep(30); /* image low optimization completion */
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/* mid-band */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x82;
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regs[R_CPD] = 0xa8;
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regs[R_CD1] = 0x66;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0xa9;
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regs[R_MD1] = 0x73;
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regs[R_MD2] = 0x1a;
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regs[R_MD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 11);
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msleep(5); /* pll locking */
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regs[R_EP1] = 0xc6;
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tda18271_write_regs(fe, R_EP1, 1);
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msleep(5); /* wanted mid measurement */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x86;
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regs[R_CPD] = 0xa8;
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regs[R_CD1] = 0x66;
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regs[R_CD2] = 0xa0;
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regs[R_CD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 7);
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msleep(5); /* pll locking */
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regs[R_EP2] = 0xdf;
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tda18271_write_regs(fe, R_EP2, 1);
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msleep(30); /* image mid optimization completion */
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/* high-band */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x83;
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regs[R_CPD] = 0x98;
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regs[R_CD1] = 0x65;
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regs[R_CD2] = 0x00;
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regs[R_CD3] = 0x00;
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regs[R_MPD] = 0x99;
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regs[R_MD1] = 0x71;
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regs[R_MD2] = 0xcd;
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regs[R_MD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 11);
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msleep(5); /* pll locking */
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regs[R_EP1] = 0xc6;
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tda18271_write_regs(fe, R_EP1, 1);
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msleep(5); /* wanted high measurement */
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regs[R_EP3] = 0x1f;
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regs[R_EP4] = 0x66;
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regs[R_EP5] = 0x87;
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regs[R_CPD] = 0x98;
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regs[R_CD1] = 0x65;
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regs[R_CD2] = 0x50;
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regs[R_CD3] = 0x00;
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tda18271_write_regs(fe, R_EP3, 7);
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msleep(5); /* pll locking */
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regs[R_EP2] = 0xdf;
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tda18271_write_regs(fe, R_EP2, 1);
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msleep(30); /* image high optimization completion */
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regs[R_EP4] = 0x64;
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tda18271_write_regs(fe, R_EP4, 1);
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regs[R_EP1] = 0xc6;
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tda18271_write_regs(fe, R_EP1, 1);
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return 0;
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}
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static int tda18271_init(struct dvb_frontend *fe)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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tda18271_read_regs(fe);
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/* test IR_CAL_OK to see if we need init */
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if ((regs[R_EP1] & 0x08) == 0)
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tda18271_init_regs(fe);
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return 0;
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}
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static int tda18271_tune(struct dvb_frontend *fe,
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u32 ifc, u32 freq, u32 bw, u8 std)
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{
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struct tda18271_priv *priv = fe->tuner_priv;
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unsigned char *regs = priv->tda18271_regs;
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u32 div, N = 0;
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u8 d, pd, val;
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tda18271_init(fe);
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dbg_info("freq = %d, ifc = %d\n", freq, ifc);
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/* RF tracking filter calibration */
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/* calculate BP_Filter */
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tda18271_calc_bp_filter(&freq, &val);
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regs[R_EP1] &= ~0x07; /* clear bp filter bits */
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regs[R_EP1] |= val;
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tda18271_write_regs(fe, R_EP1, 1);
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regs[R_EB4] &= 0x07;
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regs[R_EB4] |= 0x60;
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tda18271_write_regs(fe, R_EB4, 1);
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regs[R_EB7] = 0x60;
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tda18271_write_regs(fe, R_EB7, 1);
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regs[R_EB14] = 0x00;
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tda18271_write_regs(fe, R_EB14, 1);
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regs[R_EB20] = 0xcc;
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tda18271_write_regs(fe, R_EB20, 1);
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/* set CAL mode to RF tracking filter calibration */
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regs[R_EP4] |= 0x03;
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/* calculate CAL PLL */
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switch (priv->mode) {
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case TDA18271_ANALOG:
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N = freq - 1250000;
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break;
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case TDA18271_DIGITAL:
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N = freq + bw / 2;
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break;
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}
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tda18271_calc_cal_pll(&N, &pd, &d);
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regs[R_CPD] = pd;
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div = ((d * (N / 1000)) << 7) / 125;
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regs[R_CD1] = 0xff & (div >> 16);
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regs[R_CD2] = 0xff & (div >> 8);
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regs[R_CD3] = 0xff & div;
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/* calculate MAIN PLL */
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switch (priv->mode) {
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case TDA18271_ANALOG:
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N = freq - 250000;
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break;
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case TDA18271_DIGITAL:
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N = freq + bw / 2 + 1000000;
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break;
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}
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tda18271_calc_main_pll(&N, &pd, &d);
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regs[R_MPD] = (0x7f & pd);
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switch (priv->mode) {
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case TDA18271_ANALOG:
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regs[R_MPD] &= ~0x08;
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break;
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case TDA18271_DIGITAL:
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regs[R_MPD] |= 0x08;
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break;
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}
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div = ((d * (N / 1000)) << 7) / 125;
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regs[R_MD1] = 0xff & (div >> 16);
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regs[R_MD2] = 0xff & (div >> 8);
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regs[R_MD3] = 0xff & div;
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|
tda18271_write_regs(fe, R_EP3, 11);
|
|
msleep(5); /* RF tracking filter calibration initialization */
|
|
|
|
/* search for K,M,CO for RF Calibration */
|
|
tda18271_calc_km(&freq, &val);
|
|
|
|
regs[R_EB13] &= 0x83;
|
|
regs[R_EB13] |= val;
|
|
tda18271_write_regs(fe, R_EB13, 1);
|
|
|
|
/* search for RF_BAND */
|
|
tda18271_calc_rf_band(&freq, &val);
|
|
|
|
regs[R_EP2] &= ~0xe0; /* clear rf band bits */
|
|
regs[R_EP2] |= (val << 5);
|
|
|
|
/* search for Gain_Taper */
|
|
tda18271_calc_gain_taper(&freq, &val);
|
|
|
|
regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
|
|
regs[R_EP2] |= val;
|
|
|
|
tda18271_write_regs(fe, R_EP2, 1);
|
|
tda18271_write_regs(fe, R_EP1, 1);
|
|
tda18271_write_regs(fe, R_EP2, 1);
|
|
tda18271_write_regs(fe, R_EP1, 1);
|
|
|
|
regs[R_EB4] &= 0x07;
|
|
regs[R_EB4] |= 0x40;
|
|
tda18271_write_regs(fe, R_EB4, 1);
|
|
|
|
regs[R_EB7] = 0x40;
|
|
tda18271_write_regs(fe, R_EB7, 1);
|
|
msleep(10);
|
|
|
|
regs[R_EB20] = 0xec;
|
|
tda18271_write_regs(fe, R_EB20, 1);
|
|
msleep(60); /* RF tracking filter calibration completion */
|
|
|
|
regs[R_EP4] &= ~0x03; /* set cal mode to normal */
|
|
tda18271_write_regs(fe, R_EP4, 1);
|
|
|
|
tda18271_write_regs(fe, R_EP1, 1);
|
|
|
|
/* RF tracking filer correction for VHF_Low band */
|
|
tda18271_calc_rf_cal(&freq, &val);
|
|
|
|
/* VHF_Low band only */
|
|
if (val != 0) {
|
|
regs[R_EB14] = val;
|
|
tda18271_write_regs(fe, R_EB14, 1);
|
|
}
|
|
|
|
/* Channel Configuration */
|
|
|
|
switch (priv->mode) {
|
|
case TDA18271_ANALOG:
|
|
regs[R_EB22] = 0x2c;
|
|
break;
|
|
case TDA18271_DIGITAL:
|
|
regs[R_EB22] = 0x37;
|
|
break;
|
|
}
|
|
tda18271_write_regs(fe, R_EB22, 1);
|
|
|
|
regs[R_EP1] |= 0x40; /* set dis power level on */
|
|
|
|
/* set standard */
|
|
regs[R_EP3] &= ~0x1f; /* clear std bits */
|
|
|
|
/* see table 22 */
|
|
regs[R_EP3] |= std;
|
|
|
|
regs[R_EP4] &= ~0x03; /* set cal mode to normal */
|
|
|
|
regs[R_EP4] &= ~0x1c; /* clear if level bits */
|
|
switch (priv->mode) {
|
|
case TDA18271_ANALOG:
|
|
regs[R_MPD] &= ~0x80; /* IF notch = 0 */
|
|
break;
|
|
case TDA18271_DIGITAL:
|
|
regs[R_EP4] |= 0x04;
|
|
regs[R_MPD] |= 0x80;
|
|
break;
|
|
}
|
|
|
|
regs[R_EP4] &= ~0x80; /* turn this bit on only for fm */
|
|
|
|
/* image rejection validity EP5[2:0] */
|
|
tda18271_calc_ir_measure(&freq, &val);
|
|
|
|
regs[R_EP5] &= ~0x07;
|
|
regs[R_EP5] |= val;
|
|
|
|
/* calculate MAIN PLL */
|
|
N = freq + ifc;
|
|
|
|
tda18271_calc_main_pll(&N, &pd, &d);
|
|
|
|
regs[R_MPD] = (0x7f & pd);
|
|
switch (priv->mode) {
|
|
case TDA18271_ANALOG:
|
|
regs[R_MPD] &= ~0x08;
|
|
break;
|
|
case TDA18271_DIGITAL:
|
|
regs[R_MPD] |= 0x08;
|
|
break;
|
|
}
|
|
|
|
div = ((d * (N / 1000)) << 7) / 125;
|
|
regs[R_MD1] = 0xff & (div >> 16);
|
|
regs[R_MD2] = 0xff & (div >> 8);
|
|
regs[R_MD3] = 0xff & div;
|
|
|
|
tda18271_write_regs(fe, R_TM, 15);
|
|
msleep(5);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* ------------------------------------------------------------------ */
|
|
|
|
static int tda18271_set_params(struct dvb_frontend *fe,
|
|
struct dvb_frontend_parameters *params)
|
|
{
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
u8 std;
|
|
u32 bw, sgIF = 0;
|
|
|
|
u32 freq = params->frequency;
|
|
|
|
priv->mode = TDA18271_DIGITAL;
|
|
|
|
/* see table 22 */
|
|
if (fe->ops.info.type == FE_ATSC) {
|
|
switch (params->u.vsb.modulation) {
|
|
case VSB_8:
|
|
case VSB_16:
|
|
std = 0x1b; /* device-specific (spec says 0x1c) */
|
|
sgIF = 5380000;
|
|
break;
|
|
case QAM_64:
|
|
case QAM_256:
|
|
std = 0x18; /* device-specific (spec says 0x1d) */
|
|
sgIF = 4000000;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "%s: modulation not set!\n",
|
|
__FUNCTION__);
|
|
return -EINVAL;
|
|
}
|
|
#if 0
|
|
/* userspace request is already center adjusted */
|
|
freq += 1750000; /* Adjust to center (+1.75MHZ) */
|
|
#endif
|
|
bw = 6000000;
|
|
} else if (fe->ops.info.type == FE_OFDM) {
|
|
switch (params->u.ofdm.bandwidth) {
|
|
case BANDWIDTH_6_MHZ:
|
|
std = 0x1b; /* device-specific (spec says 0x1c) */
|
|
bw = 6000000;
|
|
sgIF = 3300000;
|
|
break;
|
|
case BANDWIDTH_7_MHZ:
|
|
std = 0x19; /* device-specific (spec says 0x1d) */
|
|
bw = 7000000;
|
|
sgIF = 3800000;
|
|
break;
|
|
case BANDWIDTH_8_MHZ:
|
|
std = 0x1a; /* device-specific (spec says 0x1e) */
|
|
bw = 8000000;
|
|
sgIF = 4300000;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "%s: bandwidth not set!\n",
|
|
__FUNCTION__);
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
printk(KERN_WARNING "%s: modulation type not supported!\n",
|
|
__FUNCTION__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return tda18271_tune(fe, sgIF, freq, bw, std);
|
|
}
|
|
|
|
static int tda18271_set_analog_params(struct dvb_frontend *fe,
|
|
struct analog_parameters *params)
|
|
{
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
u8 std;
|
|
unsigned int sgIF;
|
|
char *mode;
|
|
|
|
priv->mode = TDA18271_ANALOG;
|
|
|
|
/* see table 22 */
|
|
if (params->std & V4L2_STD_MN) {
|
|
std = 0x0d;
|
|
sgIF = 92;
|
|
mode = "MN";
|
|
} else if (params->std & V4L2_STD_B) {
|
|
std = 0x0e;
|
|
sgIF = 108;
|
|
mode = "B";
|
|
} else if (params->std & V4L2_STD_GH) {
|
|
std = 0x0f;
|
|
sgIF = 124;
|
|
mode = "GH";
|
|
} else if (params->std & V4L2_STD_PAL_I) {
|
|
std = 0x0f;
|
|
sgIF = 124;
|
|
mode = "I";
|
|
} else if (params->std & V4L2_STD_DK) {
|
|
std = 0x0f;
|
|
sgIF = 124;
|
|
mode = "DK";
|
|
} else if (params->std & V4L2_STD_SECAM_L) {
|
|
std = 0x0f;
|
|
sgIF = 124;
|
|
mode = "L";
|
|
} else if (params->std & V4L2_STD_SECAM_LC) {
|
|
std = 0x0f;
|
|
sgIF = 20;
|
|
mode = "LC";
|
|
} else {
|
|
std = 0x0f;
|
|
sgIF = 124;
|
|
mode = "xx";
|
|
}
|
|
|
|
if (params->mode == V4L2_TUNER_RADIO)
|
|
sgIF = 88; /* if frequency is 5.5 MHz */
|
|
|
|
dbg_info("setting tda18271 to system %s\n", mode);
|
|
|
|
return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
|
|
0, std);
|
|
}
|
|
|
|
static int tda18271_release(struct dvb_frontend *fe)
|
|
{
|
|
kfree(fe->tuner_priv);
|
|
fe->tuner_priv = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
|
|
{
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
*frequency = priv->frequency;
|
|
return 0;
|
|
}
|
|
|
|
static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
|
|
{
|
|
struct tda18271_priv *priv = fe->tuner_priv;
|
|
*bandwidth = priv->bandwidth;
|
|
return 0;
|
|
}
|
|
|
|
static struct dvb_tuner_ops tda18271_tuner_ops = {
|
|
.info = {
|
|
.name = "NXP TDA18271HD",
|
|
.frequency_min = 45000000,
|
|
.frequency_max = 864000000,
|
|
.frequency_step = 62500
|
|
},
|
|
.init = tda18271_init,
|
|
.set_params = tda18271_set_params,
|
|
.set_analog_params = tda18271_set_analog_params,
|
|
.release = tda18271_release,
|
|
.get_frequency = tda18271_get_frequency,
|
|
.get_bandwidth = tda18271_get_bandwidth,
|
|
};
|
|
|
|
struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
|
|
struct i2c_adapter *i2c,
|
|
enum tda18271_i2c_gate gate)
|
|
{
|
|
struct tda18271_priv *priv = NULL;
|
|
|
|
dbg_info("@ %d-%04x\n", i2c_adapter_id(i2c), addr);
|
|
priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
|
|
if (priv == NULL)
|
|
return NULL;
|
|
|
|
priv->i2c_addr = addr;
|
|
priv->i2c_adap = i2c;
|
|
priv->gate = gate;
|
|
|
|
memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
|
|
sizeof(struct dvb_tuner_ops));
|
|
|
|
fe->tuner_priv = priv;
|
|
|
|
tda18271_init_regs(fe);
|
|
|
|
return fe;
|
|
}
|
|
EXPORT_SYMBOL_GPL(tda18271_attach);
|
|
MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
|
|
MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
/*
|
|
* Overrides for Emacs so that we follow Linus's tabbing style.
|
|
* ---------------------------------------------------------------------------
|
|
* Local variables:
|
|
* c-basic-offset: 8
|
|
* End:
|
|
*/
|