forked from Minki/linux
441 lines
14 KiB
C
441 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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*
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* Portions of this file are derived from the ipw3945 project, as well
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* as portions of the ieee80211 subsystem header files.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#ifndef __iwl_trans_int_pcie_h__
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#define __iwl_trans_int_pcie_h__
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/skbuff.h>
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#include <linux/wait.h>
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#include <linux/pci.h>
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#include <linux/timer.h>
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#include "iwl-fh.h"
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#include "iwl-csr.h"
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#include "iwl-trans.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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#include "iwl-op-mode.h"
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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* trans_pcie layer */
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struct iwl_rx_mem_buffer {
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dma_addr_t page_dma;
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struct page *page;
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struct list_head list;
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};
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/**
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* struct isr_statistics - interrupt statistics
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*
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*/
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struct isr_statistics {
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u32 hw;
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u32 sw;
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u32 err_code;
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u32 sch;
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u32 alive;
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u32 rfkill;
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u32 ctkill;
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u32 wakeup;
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u32 rx;
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u32 tx;
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u32 unhandled;
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};
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/**
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* struct iwl_rx_queue - Rx queue
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @pool:
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* @queue:
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @write_actual:
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* @rx_free: list of free SKBs for use
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* @rx_used: List of Rx buffers with no SKB
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rx_queue {
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__le32 *bd;
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dma_addr_t bd_dma;
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struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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u32 read;
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u32 write;
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u32 free_count;
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u32 write_actual;
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struct list_head rx_free;
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struct list_head rx_used;
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int need_update;
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struct iwl_rb_status *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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};
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struct iwl_dma_ptr {
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dma_addr_t dma;
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void *addr;
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size_t size;
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};
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/**
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* iwl_queue_inc_wrap - increment queue index, wrap back to beginning
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* @index -- current index
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* @n_bd -- total number of entries in queue (must be power of 2)
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*/
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static inline int iwl_queue_inc_wrap(int index, int n_bd)
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{
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return ++index & (n_bd - 1);
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}
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/**
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* iwl_queue_dec_wrap - decrement queue index, wrap back to end
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* @index -- current index
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* @n_bd -- total number of entries in queue (must be power of 2)
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*/
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static inline int iwl_queue_dec_wrap(int index, int n_bd)
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{
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return --index & (n_bd - 1);
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}
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struct iwl_cmd_meta {
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/* only for SYNC commands, iff the reply skb is wanted */
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struct iwl_host_cmd *source;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 flags;
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};
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/*
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* Generic queue structure
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*
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* Contains common data for Rx and Tx queues.
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*
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* Note the difference between n_bd and n_window: the hardware
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* always assumes 256 descriptors, so n_bd is always 256 (unless
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* there might be HW changes in the future). For the normal TX
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* queues, n_window, which is the size of the software queue data
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* is also 256; however, for the command queue, n_window is only
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* 32 since we don't need so many commands pending. Since the HW
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* still uses 256 BDs for DMA though, n_bd stays 256. As a result,
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* the software buffers (in the variables @meta, @txb in struct
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* iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
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* in the same struct) have 256.
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* This means that we end up with the following:
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* HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
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* SW entries: | 0 | ... | 31 |
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* where N is a number between 0 and 7. This means that the SW
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* data is a window overlayed over the HW queue.
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*/
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struct iwl_queue {
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int n_bd; /* number of BDs in this queue */
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int write_ptr; /* 1-st empty entry (index) host_w*/
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int read_ptr; /* last used entry (index) host_r*/
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/* use for monitoring and recovering the stuck queue */
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dma_addr_t dma_addr; /* physical addr for BD's */
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int n_window; /* safe queue window */
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u32 id;
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int low_mark; /* low watermark, resume queue if free
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* space more than this */
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int high_mark; /* high watermark, stop queue if free
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* space less than this */
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};
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#define TFD_TX_CMD_SLOTS 256
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#define TFD_CMD_SLOTS 32
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struct iwl_pcie_tx_queue_entry {
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struct iwl_device_cmd *cmd;
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struct iwl_device_cmd *copy_cmd;
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struct sk_buff *skb;
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struct iwl_cmd_meta meta;
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};
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/**
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* struct iwl_tx_queue - Tx Queue for DMA
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* @q: generic Rx/Tx queue descriptor
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* @tfds: transmit frame descriptors (DMA memory)
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* @entries: transmit entries (driver state)
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* @lock: queue lock
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* @stuck_timer: timer that fires if queue gets stuck
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* @trans_pcie: pointer back to transport (for timer)
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* @need_update: indicates need to update read/write index
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* @active: stores if queue is active
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*
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* A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
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* descriptors) and required locking structures.
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*/
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struct iwl_tx_queue {
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struct iwl_queue q;
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struct iwl_tfd *tfds;
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struct iwl_pcie_tx_queue_entry *entries;
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spinlock_t lock;
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struct timer_list stuck_timer;
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struct iwl_trans_pcie *trans_pcie;
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u8 need_update;
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u8 active;
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};
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rx_replenish: work that will be called when buffers need to be allocated
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* @drv - pointer to iwl_drv
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* @trans: pointer to the generic transport area
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* @irq - the irq number for the device
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* @irq_requested: true when the irq has been requested
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @kw: keep warm address
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* @pci_dev: basic pci-network driver stuff
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* @hw_base: pci hardware address support
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* @ucode_write_complete: indicates that the ucode has been copied.
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* @ucode_write_waitq: wait queue for uCode load
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* @status - transport specific status flags
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* @cmd_queue - command queue number
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* @rx_buf_size_8k: 8 kB RX buffer size
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* @rx_page_order: page order for receive buffer size
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* @wd_timeout: queue watchdog timeout (jiffies)
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*/
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struct iwl_trans_pcie {
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struct iwl_rx_queue rxq;
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struct work_struct rx_replenish;
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struct iwl_trans *trans;
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struct iwl_drv *drv;
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/* INT ICT Table */
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__le32 *ict_tbl;
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dma_addr_t ict_tbl_dma;
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int ict_index;
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u32 inta;
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bool use_ict;
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bool irq_requested;
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struct tasklet_struct irq_tasklet;
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struct isr_statistics isr_stats;
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unsigned int irq;
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spinlock_t irq_lock;
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u32 inta_mask;
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u32 scd_base_addr;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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struct iwl_tx_queue *txq;
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unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
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unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
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/* PCI bus related data */
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struct pci_dev *pci_dev;
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void __iomem *hw_base;
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bool ucode_write_complete;
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wait_queue_head_t ucode_write_waitq;
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unsigned long status;
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u8 cmd_queue;
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u8 cmd_fifo;
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u8 n_no_reclaim_cmds;
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u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
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bool rx_buf_size_8k;
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u32 rx_page_order;
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const char **command_names;
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/* queue watchdog */
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unsigned long wd_timeout;
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};
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/*****************************************************
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* DRIVER STATUS FUNCTIONS
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******************************************************/
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#define STATUS_HCMD_ACTIVE 0
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#define STATUS_DEVICE_ENABLED 1
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#define STATUS_TPOWER_PMI 2
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#define STATUS_INT_ENABLED 3
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#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
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((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
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static inline struct iwl_trans *
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iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
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{
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return container_of((void *)trans_pcie, struct iwl_trans,
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trans_specific);
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}
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struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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const struct pci_device_id *ent,
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const struct iwl_cfg *cfg);
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void iwl_trans_pcie_free(struct iwl_trans *trans);
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/*****************************************************
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* RX
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******************************************************/
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void iwl_bg_rx_replenish(struct work_struct *data);
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void iwl_irq_tasklet(struct iwl_trans *trans);
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void iwlagn_rx_replenish(struct iwl_trans *trans);
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void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
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struct iwl_rx_queue *q);
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/*****************************************************
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* ICT
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******************************************************/
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void iwl_reset_ict(struct iwl_trans *trans);
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void iwl_disable_ict(struct iwl_trans *trans);
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int iwl_alloc_isr_ict(struct iwl_trans *trans);
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void iwl_free_isr_ict(struct iwl_trans *trans);
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irqreturn_t iwl_isr_ict(int irq, void *data);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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void iwl_txq_update_write_ptr(struct iwl_trans *trans,
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struct iwl_tx_queue *txq);
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int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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dma_addr_t addr, u16 len, u8 reset);
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int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
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int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_tx_cmd_complete(struct iwl_trans *trans,
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struct iwl_rx_cmd_buffer *rxb, int handler_status);
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void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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u16 byte_cnt);
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void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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int sta_id, int tid, int frame_limit, u16 ssn);
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
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void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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enum dma_data_direction dma_dir);
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int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
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struct sk_buff_head *skbs);
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int iwl_queue_space(const struct iwl_queue *q);
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/*****************************************************
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* Error handling
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******************************************************/
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int iwl_dump_fh(struct iwl_trans *trans, char **buf);
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void iwl_dump_csr(struct iwl_trans *trans);
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/*****************************************************
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* Helpers
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******************************************************/
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static inline void iwl_disable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
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/* disable interrupts from uCode/NIC to host */
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iwl_write32(trans, CSR_INT_MASK, 0x00000000);
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/* acknowledge/clear/reset any interrupts still pending
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* from uCode or flow handler (Rx/Tx DMA) */
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iwl_write32(trans, CSR_INT, 0xffffffff);
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iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
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IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
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}
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static inline void iwl_enable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
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set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
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iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
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}
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static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
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{
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IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
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iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
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}
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static inline void iwl_wake_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) {
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IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id);
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iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id);
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}
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}
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static inline void iwl_stop_queue(struct iwl_trans *trans,
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struct iwl_tx_queue *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) {
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iwl_op_mode_queue_full(trans->op_mode, txq->q.id);
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IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id);
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} else
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IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
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txq->q.id);
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}
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static inline int iwl_queue_used(const struct iwl_queue *q, int i)
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{
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return q->write_ptr >= q->read_ptr ?
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(i >= q->read_ptr && i < q->write_ptr) :
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!(i < q->read_ptr && i >= q->write_ptr);
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}
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static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
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{
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return index & (q->n_window - 1);
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}
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static inline const char *
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trans_pcie_get_cmd_string(struct iwl_trans_pcie *trans_pcie, u8 cmd)
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{
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if (!trans_pcie->command_names || !trans_pcie->command_names[cmd])
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return "UNKNOWN";
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return trans_pcie->command_names[cmd];
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}
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static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
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{
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return !(iwl_read32(trans, CSR_GP_CNTRL) &
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CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
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}
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#endif /* __iwl_trans_int_pcie_h__ */
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