Anup Patel fac3725364 KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table ... Supporting hardware updates of PTE A and D bits is optional for any RISC-V implementation so current software strategy is to always set these bits in both G-stage (hypervisor) and VS-stage (guest kernel). If PTE A and D bits are not set by software (hypervisor or guest) then RISC-V implementations not supporting hardware updates of these bits will cause traps even for perfectly valid PTEs. Based on above explanation, the VS-stage page table created by various KVM selftest applications is not correct because PTE A and D bits are not set. This patch fixes VS-stage page table programming of PTE A and D bits for KVM selftests. Fixes: 3e06cdf105 ("KVM: selftests: Add initial support for RISC-V 64-bit") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>		2022-04-09 09:15:44 +05:30
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cxl	tools/testing/cxl: Add a physical_node link	2022-02-08 22:57:33 -08:00
fault-injection
ktest
kunit	linux-kselftest-kunit-5.18-rc1	2022-03-23 12:56:39 -07:00
memblock	memblock tests: Add TODO and README files	2022-03-10 12:19:44 +02:00
nvdimm	nvdimm/region: Delete nd_blk_region infrastructure	2022-03-11 15:53:13 -08:00
radix-tree	tools: Move gfp.h and slab.h from radix-tree to lib	2022-02-20 08:44:37 +02:00
scatterlist	tools/testing/scatterlist: add missing defines	2022-01-30 09:56:58 +02:00
selftests	KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table	2022-04-09 09:15:44 +05:30
vsock	af_vsock: SOCK_SEQPACKET broken buffer test	2022-03-18 15:13:19 +00:00