Giulio Benetti fa4127c5eb drm/sun4i: fix HSYNC and VSYNC polarity ... Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0. Invert their settings of IO_POL register. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/1518717288-123578-1-git-send-email-giulio.benetti@micronovasrl.com		2018-02-16 21:16:03 +01:00
..
drm	drm/sun4i: fix HSYNC and VSYNC polarity	2018-02-16 21:16:03 +01:00
host1x	gpu: host1x: Use IOMMU groups	2017-12-21 14:52:36 +01:00
ipu-v3	gpu: ipu-v3: allow to build with COMPILE_TEST	2017-12-19 12:49:11 +01:00
vga	vgaarb: Factor out EFI and fallback default device selection	2017-10-18 10:04:56 +02:00
Makefile