fa1fc24662
The ColdFire QSPI is common to quite a few ColdFire CPUs. No need to duplicate its platform setup code for every CPU family member that has it. Merge all the setup code into a single shared file. This also results in few platforms no longer needing any local platform setup code. In those cases remove the empty devices array and initcall code as well. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/527x/config.c
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*
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* Sub-architcture dependent initialization code for the Freescale
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* 5270/5271 CPUs.
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*
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* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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/***************************************************************************/
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#ifdef CONFIG_SPI_COLDFIRE_QSPI
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static void __init m527x_qspi_init(void)
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{
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#if defined(CONFIG_M5271)
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u16 par;
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/* setup QSPS pins for QSPI with gpio CS control */
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writeb(0x1f, MCFGPIO_PAR_QSPI);
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/* and CS2 & CS3 as gpio */
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par = readw(MCFGPIO_PAR_TIMER);
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par &= 0x3f3f;
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writew(par, MCFGPIO_PAR_TIMER);
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#elif defined(CONFIG_M5275)
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/* setup QSPS pins for QSPI with gpio CS control */
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writew(0x003e, MCFGPIO_PAR_QSPI);
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#endif
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}
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#endif /* CONFIG_SPI_COLDFIRE_QSPI */
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/***************************************************************************/
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static void __init m527x_uarts_init(void)
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{
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u16 sepmask;
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/*
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* External Pin Mask Setting & Enable External Pin for Interface
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*/
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sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
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sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
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writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
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}
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/***************************************************************************/
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static void __init m527x_fec_init(void)
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{
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u16 par;
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u8 v;
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/* Set multi-function pins to ethernet mode for fec0 */
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#if defined(CONFIG_M5271)
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v = readb(MCF_IPSBAR + 0x100047);
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writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
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#else
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par = readw(MCF_IPSBAR + 0x100082);
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writew(par | 0xf00, MCF_IPSBAR + 0x100082);
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v = readb(MCF_IPSBAR + 0x100078);
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writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
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#endif
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#ifdef CONFIG_FEC2
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/* Set multi-function pins to ethernet mode for fec1 */
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par = readw(MCF_IPSBAR + 0x100082);
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writew(par | 0xa0, MCF_IPSBAR + 0x100082);
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v = readb(MCF_IPSBAR + 0x100079);
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writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
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#endif
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}
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/***************************************************************************/
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static void m527x_cpu_reset(void)
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{
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local_irq_disable();
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__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = m527x_cpu_reset;
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mach_sched_init = hw_timer_init;
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m527x_uarts_init();
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m527x_fec_init();
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#ifdef CONFIG_SPI_COLDFIRE_QSPI
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m527x_qspi_init();
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#endif
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}
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/***************************************************************************/
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