forked from Minki/linux
3dc638d13a
This patch adds set_rx_int_on_com function for interrupt when dma is completed. Signed-off-by: Byungho An <bh74.an@samsung.com> Signed-off-by: David S. Miller <davem@davemloft.net>
523 lines
13 KiB
C
523 lines
13 KiB
C
/* 10G controller driver for Samsung SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Siva Reddy Kallam <siva.kallam@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include "sxgbe_common.h"
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#include "sxgbe_dma.h"
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#include "sxgbe_desc.h"
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/* DMA TX descriptor ring initialization */
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static void sxgbe_init_tx_desc(struct sxgbe_tx_norm_desc *p)
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{
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p->tdes23.tx_rd_des23.own_bit = 0;
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}
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static void sxgbe_tx_desc_enable_tse(struct sxgbe_tx_norm_desc *p, u8 is_tse,
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u32 total_hdr_len, u32 tcp_hdr_len,
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u32 tcp_payload_len)
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{
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p->tdes23.tx_rd_des23.tse_bit = is_tse;
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p->tdes23.tx_rd_des23.buf1_size = total_hdr_len;
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p->tdes23.tx_rd_des23.tcp_hdr_len = tcp_hdr_len / 4;
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p->tdes23.tx_rd_des23.tx_pkt_len.tcp_payload_len = tcp_payload_len;
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}
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/* Assign buffer lengths for descriptor */
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static void sxgbe_prepare_tx_desc(struct sxgbe_tx_norm_desc *p, u8 is_fd,
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int buf1_len, int pkt_len, int cksum)
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{
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p->tdes23.tx_rd_des23.first_desc = is_fd;
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p->tdes23.tx_rd_des23.buf1_size = buf1_len;
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p->tdes23.tx_rd_des23.tx_pkt_len.pkt_len.total_pkt_len = pkt_len;
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if (cksum)
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p->tdes23.tx_rd_des23.cksum_ctl = cic_full;
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}
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/* Set VLAN control information */
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static void sxgbe_tx_vlanctl_desc(struct sxgbe_tx_norm_desc *p, int vlan_ctl)
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{
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p->tdes23.tx_rd_des23.vlan_tag_ctl = vlan_ctl;
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}
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/* Set the owner of Normal descriptor */
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static void sxgbe_set_tx_owner(struct sxgbe_tx_norm_desc *p)
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{
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p->tdes23.tx_rd_des23.own_bit = 1;
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}
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/* Get the owner of Normal descriptor */
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static int sxgbe_get_tx_owner(struct sxgbe_tx_norm_desc *p)
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{
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return p->tdes23.tx_rd_des23.own_bit;
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}
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/* Invoked by the xmit function to close the tx descriptor */
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static void sxgbe_close_tx_desc(struct sxgbe_tx_norm_desc *p)
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{
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p->tdes23.tx_rd_des23.last_desc = 1;
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p->tdes23.tx_rd_des23.int_on_com = 1;
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}
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/* Clean the tx descriptor as soon as the tx irq is received */
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static void sxgbe_release_tx_desc(struct sxgbe_tx_norm_desc *p)
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{
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memset(p, 0, sizeof(*p));
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}
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/* Clear interrupt on tx frame completion. When this bit is
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* set an interrupt happens as soon as the frame is transmitted
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*/
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static void sxgbe_clear_tx_ic(struct sxgbe_tx_norm_desc *p)
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{
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p->tdes23.tx_rd_des23.int_on_com = 0;
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}
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/* Last tx segment reports the transmit status */
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static int sxgbe_get_tx_ls(struct sxgbe_tx_norm_desc *p)
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{
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return p->tdes23.tx_rd_des23.last_desc;
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}
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/* Get the buffer size from the descriptor */
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static int sxgbe_get_tx_len(struct sxgbe_tx_norm_desc *p)
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{
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return p->tdes23.tx_rd_des23.buf1_size;
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}
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/* Set tx timestamp enable bit */
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static void sxgbe_tx_enable_tstamp(struct sxgbe_tx_norm_desc *p)
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{
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p->tdes23.tx_rd_des23.timestmp_enable = 1;
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}
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/* get tx timestamp status */
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static int sxgbe_get_tx_timestamp_status(struct sxgbe_tx_norm_desc *p)
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{
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return p->tdes23.tx_rd_des23.timestmp_enable;
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}
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/* TX Context Descripto Specific */
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static void sxgbe_tx_ctxt_desc_set_ctxt(struct sxgbe_tx_ctxt_desc *p)
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{
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p->ctxt_bit = 1;
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}
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/* Set the owner of TX context descriptor */
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static void sxgbe_tx_ctxt_desc_set_owner(struct sxgbe_tx_ctxt_desc *p)
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{
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p->own_bit = 1;
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}
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/* Get the owner of TX context descriptor */
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static int sxgbe_tx_ctxt_desc_get_owner(struct sxgbe_tx_ctxt_desc *p)
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{
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return p->own_bit;
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}
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/* Set TX mss in TX context Descriptor */
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static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, u16 mss)
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{
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p->maxseg_size = mss;
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}
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/* Get TX mss from TX context Descriptor */
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static int sxgbe_tx_ctxt_desc_get_mss(struct sxgbe_tx_ctxt_desc *p)
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{
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return p->maxseg_size;
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}
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/* Set TX tcmssv in TX context Descriptor */
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static void sxgbe_tx_ctxt_desc_set_tcmssv(struct sxgbe_tx_ctxt_desc *p)
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{
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p->tcmssv = 1;
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}
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/* Reset TX ostc in TX context Descriptor */
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static void sxgbe_tx_ctxt_desc_reset_ostc(struct sxgbe_tx_ctxt_desc *p)
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{
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p->ostc = 0;
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}
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/* Set IVLAN information */
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static void sxgbe_tx_ctxt_desc_set_ivlantag(struct sxgbe_tx_ctxt_desc *p,
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int is_ivlanvalid, int ivlan_tag,
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int ivlan_ctl)
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{
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if (is_ivlanvalid) {
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p->ivlan_tag_valid = is_ivlanvalid;
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p->ivlan_tag = ivlan_tag;
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p->ivlan_tag_ctl = ivlan_ctl;
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}
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}
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/* Return IVLAN Tag */
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static int sxgbe_tx_ctxt_desc_get_ivlantag(struct sxgbe_tx_ctxt_desc *p)
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{
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return p->ivlan_tag;
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}
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/* Set VLAN Tag */
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static void sxgbe_tx_ctxt_desc_set_vlantag(struct sxgbe_tx_ctxt_desc *p,
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int is_vlanvalid, int vlan_tag)
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{
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if (is_vlanvalid) {
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p->vltag_valid = is_vlanvalid;
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p->vlan_tag = vlan_tag;
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}
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}
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/* Return VLAN Tag */
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static int sxgbe_tx_ctxt_desc_get_vlantag(struct sxgbe_tx_ctxt_desc *p)
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{
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return p->vlan_tag;
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}
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/* Set Time stamp */
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static void sxgbe_tx_ctxt_desc_set_tstamp(struct sxgbe_tx_ctxt_desc *p,
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u8 ostc_enable, u64 tstamp)
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{
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if (ostc_enable) {
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p->ostc = ostc_enable;
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p->tstamp_lo = (u32) tstamp;
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p->tstamp_hi = (u32) (tstamp>>32);
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}
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}
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/* Close TX context descriptor */
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static void sxgbe_tx_ctxt_desc_close(struct sxgbe_tx_ctxt_desc *p)
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{
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p->own_bit = 1;
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}
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/* WB status of context descriptor */
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static int sxgbe_tx_ctxt_desc_get_cde(struct sxgbe_tx_ctxt_desc *p)
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{
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return p->ctxt_desc_err;
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}
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/* DMA RX descriptor ring initialization */
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static void sxgbe_init_rx_desc(struct sxgbe_rx_norm_desc *p, int disable_rx_ic,
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int mode, int end)
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{
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p->rdes23.rx_rd_des23.own_bit = 1;
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if (disable_rx_ic)
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p->rdes23.rx_rd_des23.int_on_com = disable_rx_ic;
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}
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/* Get RX own bit */
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static int sxgbe_get_rx_owner(struct sxgbe_rx_norm_desc *p)
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{
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return p->rdes23.rx_rd_des23.own_bit;
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}
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/* Set RX own bit */
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static void sxgbe_set_rx_owner(struct sxgbe_rx_norm_desc *p)
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{
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p->rdes23.rx_rd_des23.own_bit = 1;
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}
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/* Set Interrupt on completion bit */
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static void sxgbe_set_rx_int_on_com(struct sxgbe_rx_norm_desc *p)
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{
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p->rdes23.rx_rd_des23.int_on_com = 1;
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}
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/* Get the receive frame size */
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static int sxgbe_get_rx_frame_len(struct sxgbe_rx_norm_desc *p)
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{
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return p->rdes23.rx_wb_des23.pkt_len;
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}
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/* Return first Descriptor status */
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static int sxgbe_get_rx_fd_status(struct sxgbe_rx_norm_desc *p)
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{
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return p->rdes23.rx_wb_des23.first_desc;
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}
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/* Return Last Descriptor status */
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static int sxgbe_get_rx_ld_status(struct sxgbe_rx_norm_desc *p)
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{
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return p->rdes23.rx_wb_des23.last_desc;
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}
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/* Return the RX status looking at the WB fields */
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static int sxgbe_rx_wbstatus(struct sxgbe_rx_norm_desc *p,
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struct sxgbe_extra_stats *x, int *checksum)
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{
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int status = 0;
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*checksum = CHECKSUM_UNNECESSARY;
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if (p->rdes23.rx_wb_des23.err_summary) {
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switch (p->rdes23.rx_wb_des23.err_l2_type) {
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case RX_GMII_ERR:
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status = -EINVAL;
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x->rx_code_gmii_err++;
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break;
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case RX_WATCHDOG_ERR:
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status = -EINVAL;
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x->rx_watchdog_err++;
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break;
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case RX_CRC_ERR:
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status = -EINVAL;
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x->rx_crc_err++;
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break;
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case RX_GAINT_ERR:
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status = -EINVAL;
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x->rx_gaint_pkt_err++;
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break;
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case RX_IP_HDR_ERR:
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*checksum = CHECKSUM_NONE;
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x->ip_hdr_err++;
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break;
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case RX_PAYLOAD_ERR:
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*checksum = CHECKSUM_NONE;
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x->ip_payload_err++;
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break;
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case RX_OVERFLOW_ERR:
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status = -EINVAL;
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x->overflow_error++;
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break;
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default:
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pr_err("Invalid Error type\n");
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break;
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}
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} else {
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switch (p->rdes23.rx_wb_des23.err_l2_type) {
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case RX_LEN_PKT:
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x->len_pkt++;
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break;
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case RX_MACCTL_PKT:
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x->mac_ctl_pkt++;
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break;
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case RX_DCBCTL_PKT:
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x->dcb_ctl_pkt++;
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break;
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case RX_ARP_PKT:
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x->arp_pkt++;
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break;
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case RX_OAM_PKT:
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x->oam_pkt++;
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break;
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case RX_UNTAG_PKT:
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x->untag_okt++;
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break;
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case RX_OTHER_PKT:
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x->other_pkt++;
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break;
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case RX_SVLAN_PKT:
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x->svlan_tag_pkt++;
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break;
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case RX_CVLAN_PKT:
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x->cvlan_tag_pkt++;
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break;
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case RX_DVLAN_OCVLAN_ICVLAN_PKT:
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x->dvlan_ocvlan_icvlan_pkt++;
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break;
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case RX_DVLAN_OSVLAN_ISVLAN_PKT:
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x->dvlan_osvlan_isvlan_pkt++;
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break;
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case RX_DVLAN_OSVLAN_ICVLAN_PKT:
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x->dvlan_osvlan_icvlan_pkt++;
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break;
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case RX_DVLAN_OCVLAN_ISVLAN_PKT:
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x->dvlan_ocvlan_icvlan_pkt++;
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break;
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default:
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pr_err("Invalid L2 Packet type\n");
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break;
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}
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}
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/* L3/L4 Pkt type */
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switch (p->rdes23.rx_wb_des23.layer34_pkt_type) {
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case RX_NOT_IP_PKT:
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x->not_ip_pkt++;
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break;
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case RX_IPV4_TCP_PKT:
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x->ip4_tcp_pkt++;
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break;
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case RX_IPV4_UDP_PKT:
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x->ip4_udp_pkt++;
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break;
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case RX_IPV4_ICMP_PKT:
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x->ip4_icmp_pkt++;
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break;
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case RX_IPV4_UNKNOWN_PKT:
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x->ip4_unknown_pkt++;
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break;
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case RX_IPV6_TCP_PKT:
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x->ip6_tcp_pkt++;
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break;
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case RX_IPV6_UDP_PKT:
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x->ip6_udp_pkt++;
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break;
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case RX_IPV6_ICMP_PKT:
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x->ip6_icmp_pkt++;
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break;
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case RX_IPV6_UNKNOWN_PKT:
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x->ip6_unknown_pkt++;
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break;
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default:
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pr_err("Invalid L3/L4 Packet type\n");
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break;
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}
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/* Filter */
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if (p->rdes23.rx_wb_des23.vlan_filter_match)
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x->vlan_filter_match++;
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if (p->rdes23.rx_wb_des23.sa_filter_fail) {
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status = -EINVAL;
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x->sa_filter_fail++;
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}
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if (p->rdes23.rx_wb_des23.da_filter_fail) {
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status = -EINVAL;
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x->da_filter_fail++;
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}
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if (p->rdes23.rx_wb_des23.hash_filter_pass)
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x->hash_filter_pass++;
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if (p->rdes23.rx_wb_des23.l3_filter_match)
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x->l3_filter_match++;
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if (p->rdes23.rx_wb_des23.l4_filter_match)
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x->l4_filter_match++;
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return status;
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}
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/* Get own bit of context descriptor */
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static int sxgbe_get_rx_ctxt_owner(struct sxgbe_rx_ctxt_desc *p)
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{
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return p->own_bit;
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}
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/* Set own bit for context descriptor */
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static void sxgbe_set_ctxt_rx_owner(struct sxgbe_rx_ctxt_desc *p)
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{
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p->own_bit = 1;
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}
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/* Return the reception status looking at Context control information */
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static void sxgbe_rx_ctxt_wbstatus(struct sxgbe_rx_ctxt_desc *p,
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struct sxgbe_extra_stats *x)
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{
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if (p->tstamp_dropped)
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x->timestamp_dropped++;
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/* ptp */
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if (p->ptp_msgtype == RX_NO_PTP)
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x->rx_msg_type_no_ptp++;
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else if (p->ptp_msgtype == RX_PTP_SYNC)
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x->rx_ptp_type_sync++;
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else if (p->ptp_msgtype == RX_PTP_FOLLOW_UP)
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x->rx_ptp_type_follow_up++;
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else if (p->ptp_msgtype == RX_PTP_DELAY_REQ)
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x->rx_ptp_type_delay_req++;
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else if (p->ptp_msgtype == RX_PTP_DELAY_RESP)
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x->rx_ptp_type_delay_resp++;
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else if (p->ptp_msgtype == RX_PTP_PDELAY_REQ)
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x->rx_ptp_type_pdelay_req++;
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else if (p->ptp_msgtype == RX_PTP_PDELAY_RESP)
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x->rx_ptp_type_pdelay_resp++;
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else if (p->ptp_msgtype == RX_PTP_PDELAY_FOLLOW_UP)
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x->rx_ptp_type_pdelay_follow_up++;
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else if (p->ptp_msgtype == RX_PTP_ANNOUNCE)
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x->rx_ptp_announce++;
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else if (p->ptp_msgtype == RX_PTP_MGMT)
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x->rx_ptp_mgmt++;
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else if (p->ptp_msgtype == RX_PTP_SIGNAL)
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x->rx_ptp_signal++;
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else if (p->ptp_msgtype == RX_PTP_RESV_MSG)
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x->rx_ptp_resv_msg_type++;
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}
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/* Get rx timestamp status */
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static int sxgbe_get_rx_ctxt_tstamp_status(struct sxgbe_rx_ctxt_desc *p)
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{
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if ((p->tstamp_hi == 0xffffffff) && (p->tstamp_lo == 0xffffffff)) {
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pr_err("Time stamp corrupted\n");
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return 0;
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}
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return p->tstamp_available;
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}
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static u64 sxgbe_get_rx_timestamp(struct sxgbe_rx_ctxt_desc *p)
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{
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u64 ns;
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ns = p->tstamp_lo;
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ns |= ((u64)p->tstamp_hi) << 32;
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|
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return ns;
|
|
}
|
|
|
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static const struct sxgbe_desc_ops desc_ops = {
|
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.init_tx_desc = sxgbe_init_tx_desc,
|
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.tx_desc_enable_tse = sxgbe_tx_desc_enable_tse,
|
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.prepare_tx_desc = sxgbe_prepare_tx_desc,
|
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.tx_vlanctl_desc = sxgbe_tx_vlanctl_desc,
|
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.set_tx_owner = sxgbe_set_tx_owner,
|
|
.get_tx_owner = sxgbe_get_tx_owner,
|
|
.close_tx_desc = sxgbe_close_tx_desc,
|
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.release_tx_desc = sxgbe_release_tx_desc,
|
|
.clear_tx_ic = sxgbe_clear_tx_ic,
|
|
.get_tx_ls = sxgbe_get_tx_ls,
|
|
.get_tx_len = sxgbe_get_tx_len,
|
|
.tx_enable_tstamp = sxgbe_tx_enable_tstamp,
|
|
.get_tx_timestamp_status = sxgbe_get_tx_timestamp_status,
|
|
.tx_ctxt_desc_set_ctxt = sxgbe_tx_ctxt_desc_set_ctxt,
|
|
.tx_ctxt_desc_set_owner = sxgbe_tx_ctxt_desc_set_owner,
|
|
.get_tx_ctxt_owner = sxgbe_tx_ctxt_desc_get_owner,
|
|
.tx_ctxt_desc_set_mss = sxgbe_tx_ctxt_desc_set_mss,
|
|
.tx_ctxt_desc_get_mss = sxgbe_tx_ctxt_desc_get_mss,
|
|
.tx_ctxt_desc_set_tcmssv = sxgbe_tx_ctxt_desc_set_tcmssv,
|
|
.tx_ctxt_desc_reset_ostc = sxgbe_tx_ctxt_desc_reset_ostc,
|
|
.tx_ctxt_desc_set_ivlantag = sxgbe_tx_ctxt_desc_set_ivlantag,
|
|
.tx_ctxt_desc_get_ivlantag = sxgbe_tx_ctxt_desc_get_ivlantag,
|
|
.tx_ctxt_desc_set_vlantag = sxgbe_tx_ctxt_desc_set_vlantag,
|
|
.tx_ctxt_desc_get_vlantag = sxgbe_tx_ctxt_desc_get_vlantag,
|
|
.tx_ctxt_set_tstamp = sxgbe_tx_ctxt_desc_set_tstamp,
|
|
.close_tx_ctxt_desc = sxgbe_tx_ctxt_desc_close,
|
|
.get_tx_ctxt_cde = sxgbe_tx_ctxt_desc_get_cde,
|
|
.init_rx_desc = sxgbe_init_rx_desc,
|
|
.get_rx_owner = sxgbe_get_rx_owner,
|
|
.set_rx_owner = sxgbe_set_rx_owner,
|
|
.set_rx_int_on_com = sxgbe_set_rx_int_on_com,
|
|
.get_rx_frame_len = sxgbe_get_rx_frame_len,
|
|
.get_rx_fd_status = sxgbe_get_rx_fd_status,
|
|
.get_rx_ld_status = sxgbe_get_rx_ld_status,
|
|
.rx_wbstatus = sxgbe_rx_wbstatus,
|
|
.get_rx_ctxt_owner = sxgbe_get_rx_ctxt_owner,
|
|
.set_rx_ctxt_owner = sxgbe_set_ctxt_rx_owner,
|
|
.rx_ctxt_wbstatus = sxgbe_rx_ctxt_wbstatus,
|
|
.get_rx_ctxt_tstamp_status = sxgbe_get_rx_ctxt_tstamp_status,
|
|
.get_timestamp = sxgbe_get_rx_timestamp,
|
|
};
|
|
|
|
const struct sxgbe_desc_ops *sxgbe_get_desc_ops(void)
|
|
{
|
|
return &desc_ops;
|
|
}
|