linux/drivers/gpu
Changbin Du f857269057 drm/i915/gvt: exclude cfg space from failsafe mode
When test GVTg as below scenario:
  VM boot --> failsafe --> kill qemu --> VM boot.
Qemu report error at the second boot:
  ERROR: PCI region size must be pow2 type=0x0, size=0x1fa1000

Qemu need access PCI_ROM_ADDRESS reg to determine the size of expansion
PCI rom. The mechanism just like the BAR reg (write-read) and we should
return the size 0 since we have no rom. If we reject the write to
PCI_ROM_ADDRESS, Qemu cannot get the correct size of rom.

Essentially, GVTg failsafe mode should not break PCI function. So we
exclude cfg space from failsafe mode. This can fix above issue.

v2: add Fixes and Bugzilla link.

Fixes: fd64be6367 ("drm/i915/gvt: introduced failsafe mode into vgpu")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100296
Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-30 17:47:39 +08:00
..
drm drm/i915/gvt: exclude cfg space from failsafe mode 2017-03-30 17:47:39 +08:00
host1x
ipu-v3 gpu: ipu-v3: Stop overwriting pdev->dev.of_node of child devices 2017-02-17 08:04:27 +01:00
vga sched/headers: Prepare to move signal wakeup & sigpending methods from <linux/sched.h> into <linux/sched/signal.h> 2017-03-02 08:42:32 +01:00
Makefile