f25f64ed5b
Due to index register access ordering problems, when using macros a line like this fails (and does nothing): setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); With inlined functions this line will work as expected. Note about a side effect: Seems on Geode GX1 based systems the "suspend on halt power saving feature" was never enabled due to this wrong macro expansion. With inlined functions it will be enabled, but this will stop the TSC when the CPU runs into a HLT instruction. Kernel output something like this: Clocksource tsc unstable (delta = -472746897 ns) This is the 3rd version of this patch. - Adding missed arch/i386/kernel/cpu/mtrr/state.c Thanks to Andres Salomon - Adding some big fat comments into the new header file Suggested by Andi Kleen AK: fixed x86-64 compilation Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm-i386/processor-cyrix.h>
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#include "mtrr.h"
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/* Put the processor into a state where MTRRs can be safely set */
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
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{
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unsigned int cr0;
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/* Disable interrupts locally */
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local_irq_save(ctxt->flags);
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if (use_intel() || is_cpu(CYRIX)) {
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if ( cpu_has_pge ) {
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ctxt->cr4val = read_cr4();
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write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
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}
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/* Disable and flush caches. Note that wbinvd flushes the TLBs as
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a side-effect */
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cr0 = read_cr0() | 0x40000000;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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if (use_intel())
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/* Save MTRR state */
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rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else were excluded at the top */
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ctxt->ccr3 = getCx86(CX86_CCR3);
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}
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}
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
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{
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if (use_intel())
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
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ctxt->deftype_hi);
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else if (is_cpu(CYRIX))
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/* Cyrix ARRs - everything else were excluded at the top */
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setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
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}
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/* Restore the processor after a set_mtrr_prepare */
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void set_mtrr_done(struct set_mtrr_context *ctxt)
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{
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if (use_intel() || is_cpu(CYRIX)) {
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/* Flush caches and TLBs */
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wbinvd();
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/* Restore MTRRdefType */
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if (use_intel())
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, ctxt->ccr3);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if ( cpu_has_pge )
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write_cr4(ctxt->cr4val);
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}
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/* Re-enable interrupts locally (if enabled previously) */
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local_irq_restore(ctxt->flags);
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}
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