Bert Vermeulen 324f78dfb4 mtd: spi-nor: Fix address width on flash chips > 16MB ... If a flash chip has more than 16MB capacity but its BFPT reports BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3. The check in spi_nor_set_addr_width() doesn't catch it because addr_width did get set. This fixes that check. Fixes: f9acd7fa80 ("mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths") Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20201006132346.12652-1-bert@biot.com		2020-10-28 22:37:55 +05:30
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controllers	mtd: spi-nor: intel-spi: Add support for Intel Alder Lake-S SPI serial flash	2020-09-29 18:46:20 +05:30
atmel.c
catalyst.c
core.c	mtd: spi-nor: Fix address width on flash chips > 16MB	2020-10-28 22:37:55 +05:30
core.h	Revert "mtd: spi-nor: Add capability to disable flash quad mode"	2020-09-14 20:58:27 +05:30
eon.c
esmt.c
everspin.c
fujitsu.c
gigadevice.c
intel.c
issi.c
Kconfig
macronix.c	mtd: spi-nor: macronix: Add SECT_4K to mx25l12805d	2020-09-29 18:44:27 +05:30
Makefile
micron-st.c	mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g	2020-07-27 08:37:06 +03:00
sfdp.c	mtd: spi-nor: sfdp: do not make invalid quad enable fatal	2020-07-13 10:43:19 +03:00
sfdp.h
spansion.c	mtd: spi-nor: update read capabilities for w25q64 and s25fl064k	2020-07-27 09:03:32 +03:00
sst.c
winbond.c	mtd: spi-nor: winbond: Add support for w25q64jwm	2020-09-29 18:47:11 +05:30
xilinx.c
xmc.c