forked from Minki/linux
f6168e3304
The breadcrumbs are about to be used from within IRQ context sections (e.g. nouveau signals a fence from an interrupt handler causing us to submit a new request) and/or from bottom-half tasklets (i.e. intel_lrc_irq_handler), therefore we need to employ the irqsafe spinlock variants. For example, deferring the request submission to the intel_lrc_irq_handler generates this trace: [ 66.388639] ================================= [ 66.388650] [ INFO: inconsistent lock state ] [ 66.388663] 4.9.0-rc2+ #56 Not tainted [ 66.388672] --------------------------------- [ 66.388682] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage. [ 66.388695] swapper/1/0 [HC0[0]:SC1[1]:HE0:SE0] takes: [ 66.388706] (&(&b->lock)->rlock){+.?...} , at: [<ffffffff81401c88>] intel_engine_enable_signaling+0x78/0x150 [ 66.388761] {SOFTIRQ-ON-W} state was registered at: [ 66.388772] [ 66.388783] [<ffffffff810bd842>] __lock_acquire+0x682/0x1870 [ 66.388795] [ 66.388803] [<ffffffff810bedbc>] lock_acquire+0x6c/0xb0 [ 66.388814] [ 66.388824] [<ffffffff8161753a>] _raw_spin_lock+0x2a/0x40 [ 66.388835] [ 66.388845] [<ffffffff81401e41>] intel_engine_reset_breadcrumbs+0x21/0xb0 [ 66.388857] [ 66.388866] [<ffffffff81403ae7>] gen8_init_common_ring+0x67/0x100 [ 66.388878] [ 66.388887] [<ffffffff81403b92>] gen8_init_render_ring+0x12/0x60 [ 66.388903] [ 66.388912] [<ffffffff813f8707>] i915_gem_init_hw+0xf7/0x2a0 [ 66.388927] [ 66.388936] [<ffffffff813f899b>] i915_gem_init+0xbb/0xf0 [ 66.388950] [ 66.388959] [<ffffffff813b4980>] i915_driver_load+0x7e0/0x1330 [ 66.388978] [ 66.388988] [<ffffffff813c09d8>] i915_pci_probe+0x28/0x40 [ 66.389003] [ 66.389013] [<ffffffff812fa0db>] pci_device_probe+0x8b/0xf0 [ 66.389028] [ 66.389037] [<ffffffff8147737e>] driver_probe_device+0x21e/0x430 [ 66.389056] [ 66.389065] [<ffffffff8147766e>] __driver_attach+0xde/0xe0 [ 66.389080] [ 66.389090] [<ffffffff814751ad>] bus_for_each_dev+0x5d/0x90 [ 66.389105] [ 66.389113] [<ffffffff81477799>] driver_attach+0x19/0x20 [ 66.389134] [ 66.389144] [<ffffffff81475ced>] bus_add_driver+0x15d/0x260 [ 66.389159] [ 66.389168] [<ffffffff81477e3b>] driver_register+0x5b/0xd0 [ 66.389183] [ 66.389281] [<ffffffff812fa19b>] __pci_register_driver+0x5b/0x60 [ 66.389301] [ 66.389312] [<ffffffff81aed333>] i915_init+0x3e/0x45 [ 66.389326] [ 66.389336] [<ffffffff81ac2ffa>] do_one_initcall+0x8b/0x118 [ 66.389350] [ 66.389359] [<ffffffff81ac323a>] kernel_init_freeable+0x1b3/0x23b [ 66.389378] [ 66.389387] [<ffffffff8160fc39>] kernel_init+0x9/0x100 [ 66.389402] [ 66.389411] [<ffffffff816180e7>] ret_from_fork+0x27/0x40 [ 66.389426] irq event stamp: 315865 [ 66.389438] hardirqs last enabled at (315864): [<ffffffff816178f1>] _raw_spin_unlock_irqrestore+0x31/0x50 [ 66.389469] hardirqs last disabled at (315865): [<ffffffff816176b3>] _raw_spin_lock_irqsave+0x13/0x50 [ 66.389499] softirqs last enabled at (315818): [<ffffffff8107a04c>] _local_bh_enable+0x1c/0x50 [ 66.389530] softirqs last disabled at (315819): [<ffffffff8107a50e>] irq_exit+0xbe/0xd0 [ 66.389559] [ 66.389559] other info that might help us debug this: [ 66.389580] Possible unsafe locking scenario: [ 66.389580] [ 66.389598] CPU0 [ 66.389609] ---- [ 66.389620] lock(&(&b->lock)->rlock); [ 66.389650] <Interrupt> [ 66.389661] lock(&(&b->lock)->rlock); [ 66.389690] [ 66.389690] *** DEADLOCK *** [ 66.389690] [ 66.389715] 2 locks held by swapper/1/0: [ 66.389728] #0: (&(&tl->lock)->rlock){..-...}, at: [<ffffffff81403e01>] intel_lrc_irq_handler+0x201/0x3c0 [ 66.389785] #1: (&(&req->lock)->rlock/1){..-...}, at: [<ffffffff813fc0af>] __i915_gem_request_submit+0x8f/0x170 [ 66.389854] [ 66.389854] stack backtrace: [ 66.389959] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.9.0-rc2+ #56 [ 66.389976] Hardware name: / , BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015 [ 66.389999] ffff88027fd03c58 ffffffff812beae5 ffff88027696e680 ffffffff822afe20 [ 66.390036] ffff88027fd03ca8 ffffffff810bb420 0000000000000001 0000000000000000 [ 66.390070] 0000000000000000 0000000000000006 0000000000000004 ffff88027696ee10 [ 66.390104] Call Trace: [ 66.390117] <IRQ> [ 66.390128] [<ffffffff812beae5>] dump_stack+0x68/0x93 [ 66.390147] [<ffffffff810bb420>] print_usage_bug+0x1d0/0x1e0 [ 66.390164] [<ffffffff810bb8a0>] mark_lock+0x470/0x4f0 [ 66.390181] [<ffffffff810ba9d0>] ? print_shortest_lock_dependencies+0x1b0/0x1b0 [ 66.390203] [<ffffffff810bd75d>] __lock_acquire+0x59d/0x1870 [ 66.390221] [<ffffffff810bedbc>] lock_acquire+0x6c/0xb0 [ 66.390237] [<ffffffff810bedbc>] ? lock_acquire+0x6c/0xb0 [ 66.390255] [<ffffffff81401c88>] ? intel_engine_enable_signaling+0x78/0x150 [ 66.390273] [<ffffffff8161753a>] _raw_spin_lock+0x2a/0x40 [ 66.390291] [<ffffffff81401c88>] ? intel_engine_enable_signaling+0x78/0x150 [ 66.390309] [<ffffffff81401c88>] intel_engine_enable_signaling+0x78/0x150 [ 66.390327] [<ffffffff813fc170>] __i915_gem_request_submit+0x150/0x170 [ 66.390345] [<ffffffff81403e8b>] intel_lrc_irq_handler+0x28b/0x3c0 [ 66.390363] [<ffffffff81079d97>] tasklet_action+0x57/0xc0 [ 66.390380] [<ffffffff8107a249>] __do_softirq+0x119/0x240 [ 66.390396] [<ffffffff8107a50e>] irq_exit+0xbe/0xd0 [ 66.390414] [<ffffffff8101afd5>] do_IRQ+0x65/0x110 [ 66.390431] [<ffffffff81618806>] common_interrupt+0x86/0x86 [ 66.390446] <EOI> [ 66.390457] [<ffffffff814ec6d1>] ? cpuidle_enter_state+0x151/0x200 [ 66.390480] [<ffffffff814ec7a2>] cpuidle_enter+0x12/0x20 [ 66.390498] [<ffffffff810b639e>] call_cpuidle+0x1e/0x40 [ 66.390516] [<ffffffff810b65ae>] cpu_startup_entry+0x10e/0x1f0 [ 66.390534] [<ffffffff81036133>] start_secondary+0x103/0x130 (This is split out of the defer global seqno allocation patch due to realisation that we need a more complete conversion if we want to defer request submission even further.) v2: lockdep was warning about mixed SOFTIRQ contexts not HARDIRQ contexts so we only need to use spin_lock_bh and not disable interrupts. v3: We need full irq protection as we may be called from a third party interrupt handler (via fences). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-32-chris@chris-wilson.co.uk
665 lines
20 KiB
C
665 lines
20 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/kthread.h>
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#include "i915_drv.h"
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static void intel_breadcrumbs_hangcheck(unsigned long data)
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{
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struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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if (!b->irq_enabled)
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return;
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if (time_before(jiffies, b->timeout)) {
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mod_timer(&b->hangcheck, b->timeout);
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return;
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}
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DRM_DEBUG("Hangcheck timer elapsed... %s idle\n", engine->name);
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set_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
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mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1);
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/* Ensure that even if the GPU hangs, we get woken up.
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*
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* However, note that if no one is waiting, we never notice
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* a gpu hang. Eventually, we will have to wait for a resource
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* held by the GPU and so trigger a hangcheck. In the most
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* pathological case, this will be upon memory starvation! To
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* prevent this, we also queue the hangcheck from the retire
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* worker.
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*/
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i915_queue_hangcheck(engine->i915);
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}
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static unsigned long wait_timeout(void)
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{
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return round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES);
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}
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static void intel_breadcrumbs_fake_irq(unsigned long data)
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{
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struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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/*
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* The timer persists in case we cannot enable interrupts,
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* or if we have previously seen seqno/interrupt incoherency
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* ("missed interrupt" syndrome). Here the worker will wake up
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* every jiffie in order to kick the oldest waiter to do the
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* coherent seqno check.
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*/
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if (intel_engine_wakeup(engine))
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mod_timer(&engine->breadcrumbs.fake_irq, jiffies + 1);
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}
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static void irq_enable(struct intel_engine_cs *engine)
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{
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/* Enabling the IRQ may miss the generation of the interrupt, but
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* we still need to force the barrier before reading the seqno,
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* just in case.
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*/
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engine->breadcrumbs.irq_posted = true;
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/* Caller disables interrupts */
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spin_lock(&engine->i915->irq_lock);
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engine->irq_enable(engine);
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spin_unlock(&engine->i915->irq_lock);
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}
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static void irq_disable(struct intel_engine_cs *engine)
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{
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/* Caller disables interrupts */
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spin_lock(&engine->i915->irq_lock);
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engine->irq_disable(engine);
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spin_unlock(&engine->i915->irq_lock);
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engine->breadcrumbs.irq_posted = false;
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}
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static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
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{
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struct intel_engine_cs *engine =
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container_of(b, struct intel_engine_cs, breadcrumbs);
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struct drm_i915_private *i915 = engine->i915;
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assert_spin_locked(&b->lock);
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if (b->rpm_wakelock)
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return;
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/* Since we are waiting on a request, the GPU should be busy
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* and should have its own rpm reference. For completeness,
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* record an rpm reference for ourselves to cover the
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* interrupt we unmask.
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*/
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intel_runtime_pm_get_noresume(i915);
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b->rpm_wakelock = true;
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/* No interrupts? Kick the waiter every jiffie! */
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if (intel_irqs_enabled(i915)) {
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if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
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irq_enable(engine);
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b->irq_enabled = true;
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}
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if (!b->irq_enabled ||
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test_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
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mod_timer(&b->fake_irq, jiffies + 1);
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} else {
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/* Ensure we never sleep indefinitely */
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GEM_BUG_ON(!time_after(b->timeout, jiffies));
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mod_timer(&b->hangcheck, b->timeout);
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}
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}
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static void __intel_breadcrumbs_disable_irq(struct intel_breadcrumbs *b)
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{
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struct intel_engine_cs *engine =
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container_of(b, struct intel_engine_cs, breadcrumbs);
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assert_spin_locked(&b->lock);
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if (!b->rpm_wakelock)
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return;
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if (b->irq_enabled) {
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irq_disable(engine);
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b->irq_enabled = false;
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}
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intel_runtime_pm_put(engine->i915);
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b->rpm_wakelock = false;
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}
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static inline struct intel_wait *to_wait(struct rb_node *node)
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{
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return container_of(node, struct intel_wait, node);
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}
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static inline void __intel_breadcrumbs_finish(struct intel_breadcrumbs *b,
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struct intel_wait *wait)
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{
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assert_spin_locked(&b->lock);
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/* This request is completed, so remove it from the tree, mark it as
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* complete, and *then* wake up the associated task.
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*/
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rb_erase(&wait->node, &b->waiters);
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RB_CLEAR_NODE(&wait->node);
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wake_up_process(wait->tsk); /* implicit smp_wmb() */
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}
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static bool __intel_engine_add_wait(struct intel_engine_cs *engine,
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struct intel_wait *wait)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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struct rb_node **p, *parent, *completed;
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bool first;
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u32 seqno;
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/* Insert the request into the retirement ordered list
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* of waiters by walking the rbtree. If we are the oldest
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* seqno in the tree (the first to be retired), then
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* set ourselves as the bottom-half.
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*
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* As we descend the tree, prune completed branches since we hold the
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* spinlock we know that the first_waiter must be delayed and can
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* reduce some of the sequential wake up latency if we take action
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* ourselves and wake up the completed tasks in parallel. Also, by
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* removing stale elements in the tree, we may be able to reduce the
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* ping-pong between the old bottom-half and ourselves as first-waiter.
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*/
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first = true;
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parent = NULL;
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completed = NULL;
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seqno = intel_engine_get_seqno(engine);
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/* If the request completed before we managed to grab the spinlock,
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* return now before adding ourselves to the rbtree. We let the
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* current bottom-half handle any pending wakeups and instead
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* try and get out of the way quickly.
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*/
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if (i915_seqno_passed(seqno, wait->seqno)) {
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RB_CLEAR_NODE(&wait->node);
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return first;
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}
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p = &b->waiters.rb_node;
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while (*p) {
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parent = *p;
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if (wait->seqno == to_wait(parent)->seqno) {
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/* We have multiple waiters on the same seqno, select
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* the highest priority task (that with the smallest
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* task->prio) to serve as the bottom-half for this
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* group.
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*/
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if (wait->tsk->prio > to_wait(parent)->tsk->prio) {
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p = &parent->rb_right;
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first = false;
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} else {
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p = &parent->rb_left;
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}
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} else if (i915_seqno_passed(wait->seqno,
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to_wait(parent)->seqno)) {
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p = &parent->rb_right;
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if (i915_seqno_passed(seqno, to_wait(parent)->seqno))
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completed = parent;
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else
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first = false;
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} else {
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p = &parent->rb_left;
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}
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}
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rb_link_node(&wait->node, parent, p);
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rb_insert_color(&wait->node, &b->waiters);
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GEM_BUG_ON(!first && !rcu_access_pointer(b->irq_seqno_bh));
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if (completed) {
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struct rb_node *next = rb_next(completed);
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GEM_BUG_ON(!next && !first);
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if (next && next != &wait->node) {
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GEM_BUG_ON(first);
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b->timeout = wait_timeout();
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b->first_wait = to_wait(next);
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rcu_assign_pointer(b->irq_seqno_bh, b->first_wait->tsk);
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/* As there is a delay between reading the current
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* seqno, processing the completed tasks and selecting
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* the next waiter, we may have missed the interrupt
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* and so need for the next bottom-half to wakeup.
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*
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* Also as we enable the IRQ, we may miss the
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* interrupt for that seqno, so we have to wake up
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* the next bottom-half in order to do a coherent check
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* in case the seqno passed.
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*/
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__intel_breadcrumbs_enable_irq(b);
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if (READ_ONCE(b->irq_posted))
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wake_up_process(to_wait(next)->tsk);
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}
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do {
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struct intel_wait *crumb = to_wait(completed);
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completed = rb_prev(completed);
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__intel_breadcrumbs_finish(b, crumb);
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} while (completed);
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}
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if (first) {
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GEM_BUG_ON(rb_first(&b->waiters) != &wait->node);
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b->timeout = wait_timeout();
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b->first_wait = wait;
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rcu_assign_pointer(b->irq_seqno_bh, wait->tsk);
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/* After assigning ourselves as the new bottom-half, we must
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* perform a cursory check to prevent a missed interrupt.
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* Either we miss the interrupt whilst programming the hardware,
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* or if there was a previous waiter (for a later seqno) they
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* may be woken instead of us (due to the inherent race
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* in the unlocked read of b->irq_seqno_bh in the irq handler)
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* and so we miss the wake up.
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*/
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__intel_breadcrumbs_enable_irq(b);
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}
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GEM_BUG_ON(!rcu_access_pointer(b->irq_seqno_bh));
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GEM_BUG_ON(!b->first_wait);
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GEM_BUG_ON(rb_first(&b->waiters) != &b->first_wait->node);
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return first;
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}
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bool intel_engine_add_wait(struct intel_engine_cs *engine,
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struct intel_wait *wait)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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bool first;
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spin_lock_irq(&b->lock);
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first = __intel_engine_add_wait(engine, wait);
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spin_unlock_irq(&b->lock);
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return first;
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}
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static inline bool chain_wakeup(struct rb_node *rb, int priority)
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{
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return rb && to_wait(rb)->tsk->prio <= priority;
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}
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static inline int wakeup_priority(struct intel_breadcrumbs *b,
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struct task_struct *tsk)
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{
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if (tsk == b->signaler)
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return INT_MIN;
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else
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return tsk->prio;
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}
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void intel_engine_remove_wait(struct intel_engine_cs *engine,
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struct intel_wait *wait)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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/* Quick check to see if this waiter was already decoupled from
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* the tree by the bottom-half to avoid contention on the spinlock
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* by the herd.
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*/
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if (RB_EMPTY_NODE(&wait->node))
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return;
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spin_lock_irq(&b->lock);
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if (RB_EMPTY_NODE(&wait->node))
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goto out_unlock;
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if (b->first_wait == wait) {
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const int priority = wakeup_priority(b, wait->tsk);
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struct rb_node *next;
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GEM_BUG_ON(rcu_access_pointer(b->irq_seqno_bh) != wait->tsk);
|
|
|
|
/* We are the current bottom-half. Find the next candidate,
|
|
* the first waiter in the queue on the remaining oldest
|
|
* request. As multiple seqnos may complete in the time it
|
|
* takes us to wake up and find the next waiter, we have to
|
|
* wake up that waiter for it to perform its own coherent
|
|
* completion check.
|
|
*/
|
|
next = rb_next(&wait->node);
|
|
if (chain_wakeup(next, priority)) {
|
|
/* If the next waiter is already complete,
|
|
* wake it up and continue onto the next waiter. So
|
|
* if have a small herd, they will wake up in parallel
|
|
* rather than sequentially, which should reduce
|
|
* the overall latency in waking all the completed
|
|
* clients.
|
|
*
|
|
* However, waking up a chain adds extra latency to
|
|
* the first_waiter. This is undesirable if that
|
|
* waiter is a high priority task.
|
|
*/
|
|
u32 seqno = intel_engine_get_seqno(engine);
|
|
|
|
while (i915_seqno_passed(seqno, to_wait(next)->seqno)) {
|
|
struct rb_node *n = rb_next(next);
|
|
|
|
__intel_breadcrumbs_finish(b, to_wait(next));
|
|
next = n;
|
|
if (!chain_wakeup(next, priority))
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (next) {
|
|
/* In our haste, we may have completed the first waiter
|
|
* before we enabled the interrupt. Do so now as we
|
|
* have a second waiter for a future seqno. Afterwards,
|
|
* we have to wake up that waiter in case we missed
|
|
* the interrupt, or if we have to handle an
|
|
* exception rather than a seqno completion.
|
|
*/
|
|
b->timeout = wait_timeout();
|
|
b->first_wait = to_wait(next);
|
|
rcu_assign_pointer(b->irq_seqno_bh, b->first_wait->tsk);
|
|
if (b->first_wait->seqno != wait->seqno)
|
|
__intel_breadcrumbs_enable_irq(b);
|
|
wake_up_process(b->first_wait->tsk);
|
|
} else {
|
|
b->first_wait = NULL;
|
|
rcu_assign_pointer(b->irq_seqno_bh, NULL);
|
|
__intel_breadcrumbs_disable_irq(b);
|
|
}
|
|
} else {
|
|
GEM_BUG_ON(rb_first(&b->waiters) == &wait->node);
|
|
}
|
|
|
|
GEM_BUG_ON(RB_EMPTY_NODE(&wait->node));
|
|
rb_erase(&wait->node, &b->waiters);
|
|
|
|
out_unlock:
|
|
GEM_BUG_ON(b->first_wait == wait);
|
|
GEM_BUG_ON(rb_first(&b->waiters) !=
|
|
(b->first_wait ? &b->first_wait->node : NULL));
|
|
GEM_BUG_ON(!rcu_access_pointer(b->irq_seqno_bh) ^ RB_EMPTY_ROOT(&b->waiters));
|
|
spin_unlock_irq(&b->lock);
|
|
}
|
|
|
|
static bool signal_complete(struct drm_i915_gem_request *request)
|
|
{
|
|
if (!request)
|
|
return false;
|
|
|
|
/* If another process served as the bottom-half it may have already
|
|
* signalled that this wait is already completed.
|
|
*/
|
|
if (intel_wait_complete(&request->signaling.wait))
|
|
return true;
|
|
|
|
/* Carefully check if the request is complete, giving time for the
|
|
* seqno to be visible or if the GPU hung.
|
|
*/
|
|
if (__i915_request_irq_complete(request))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static struct drm_i915_gem_request *to_signaler(struct rb_node *rb)
|
|
{
|
|
return container_of(rb, struct drm_i915_gem_request, signaling.node);
|
|
}
|
|
|
|
static void signaler_set_rtpriority(void)
|
|
{
|
|
struct sched_param param = { .sched_priority = 1 };
|
|
|
|
sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m);
|
|
}
|
|
|
|
static int intel_breadcrumbs_signaler(void *arg)
|
|
{
|
|
struct intel_engine_cs *engine = arg;
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
struct drm_i915_gem_request *request;
|
|
|
|
/* Install ourselves with high priority to reduce signalling latency */
|
|
signaler_set_rtpriority();
|
|
|
|
do {
|
|
set_current_state(TASK_INTERRUPTIBLE);
|
|
|
|
/* We are either woken up by the interrupt bottom-half,
|
|
* or by a client adding a new signaller. In both cases,
|
|
* the GPU seqno may have advanced beyond our oldest signal.
|
|
* If it has, propagate the signal, remove the waiter and
|
|
* check again with the next oldest signal. Otherwise we
|
|
* need to wait for a new interrupt from the GPU or for
|
|
* a new client.
|
|
*/
|
|
request = READ_ONCE(b->first_signal);
|
|
if (signal_complete(request)) {
|
|
/* Wake up all other completed waiters and select the
|
|
* next bottom-half for the next user interrupt.
|
|
*/
|
|
intel_engine_remove_wait(engine,
|
|
&request->signaling.wait);
|
|
|
|
local_bh_disable();
|
|
dma_fence_signal(&request->fence);
|
|
local_bh_enable(); /* kick start the tasklets */
|
|
|
|
/* Find the next oldest signal. Note that as we have
|
|
* not been holding the lock, another client may
|
|
* have installed an even older signal than the one
|
|
* we just completed - so double check we are still
|
|
* the oldest before picking the next one.
|
|
*/
|
|
spin_lock_irq(&b->lock);
|
|
if (request == b->first_signal) {
|
|
struct rb_node *rb =
|
|
rb_next(&request->signaling.node);
|
|
b->first_signal = rb ? to_signaler(rb) : NULL;
|
|
}
|
|
rb_erase(&request->signaling.node, &b->signals);
|
|
spin_unlock_irq(&b->lock);
|
|
|
|
i915_gem_request_put(request);
|
|
} else {
|
|
if (kthread_should_stop())
|
|
break;
|
|
|
|
schedule();
|
|
}
|
|
} while (1);
|
|
__set_current_state(TASK_RUNNING);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void intel_engine_enable_signaling(struct drm_i915_gem_request *request)
|
|
{
|
|
struct intel_engine_cs *engine = request->engine;
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
struct rb_node *parent, **p;
|
|
bool first, wakeup;
|
|
|
|
/* Note that we may be called from an interrupt handler on another
|
|
* device (e.g. nouveau signaling a fence completion causing us
|
|
* to submit a request, and so enable signaling). As such,
|
|
* we need to make sure that all other users of b->lock protect
|
|
* against interrupts, i.e. use spin_lock_irqsave.
|
|
*/
|
|
|
|
/* locked by dma_fence_enable_sw_signaling() (irqsafe fence->lock) */
|
|
assert_spin_locked(&request->lock);
|
|
if (!request->global_seqno)
|
|
return;
|
|
|
|
request->signaling.wait.tsk = b->signaler;
|
|
request->signaling.wait.seqno = request->global_seqno;
|
|
i915_gem_request_get(request);
|
|
|
|
spin_lock(&b->lock);
|
|
|
|
/* First add ourselves into the list of waiters, but register our
|
|
* bottom-half as the signaller thread. As per usual, only the oldest
|
|
* waiter (not just signaller) is tasked as the bottom-half waking
|
|
* up all completed waiters after the user interrupt.
|
|
*
|
|
* If we are the oldest waiter, enable the irq (after which we
|
|
* must double check that the seqno did not complete).
|
|
*/
|
|
wakeup = __intel_engine_add_wait(engine, &request->signaling.wait);
|
|
|
|
/* Now insert ourselves into the retirement ordered list of signals
|
|
* on this engine. We track the oldest seqno as that will be the
|
|
* first signal to complete.
|
|
*/
|
|
parent = NULL;
|
|
first = true;
|
|
p = &b->signals.rb_node;
|
|
while (*p) {
|
|
parent = *p;
|
|
if (i915_seqno_passed(request->global_seqno,
|
|
to_signaler(parent)->global_seqno)) {
|
|
p = &parent->rb_right;
|
|
first = false;
|
|
} else {
|
|
p = &parent->rb_left;
|
|
}
|
|
}
|
|
rb_link_node(&request->signaling.node, parent, p);
|
|
rb_insert_color(&request->signaling.node, &b->signals);
|
|
if (first)
|
|
smp_store_mb(b->first_signal, request);
|
|
|
|
spin_unlock(&b->lock);
|
|
|
|
if (wakeup)
|
|
wake_up_process(b->signaler);
|
|
}
|
|
|
|
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
struct task_struct *tsk;
|
|
|
|
spin_lock_init(&b->lock);
|
|
setup_timer(&b->fake_irq,
|
|
intel_breadcrumbs_fake_irq,
|
|
(unsigned long)engine);
|
|
setup_timer(&b->hangcheck,
|
|
intel_breadcrumbs_hangcheck,
|
|
(unsigned long)engine);
|
|
|
|
/* Spawn a thread to provide a common bottom-half for all signals.
|
|
* As this is an asynchronous interface we cannot steal the current
|
|
* task for handling the bottom-half to the user interrupt, therefore
|
|
* we create a thread to do the coherent seqno dance after the
|
|
* interrupt and then signal the waitqueue (via the dma-buf/fence).
|
|
*/
|
|
tsk = kthread_run(intel_breadcrumbs_signaler, engine,
|
|
"i915/signal:%d", engine->id);
|
|
if (IS_ERR(tsk))
|
|
return PTR_ERR(tsk);
|
|
|
|
b->signaler = tsk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cancel_fake_irq(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
|
|
del_timer_sync(&b->hangcheck);
|
|
del_timer_sync(&b->fake_irq);
|
|
clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
|
|
}
|
|
|
|
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
|
|
cancel_fake_irq(engine);
|
|
spin_lock_irq(&b->lock);
|
|
|
|
__intel_breadcrumbs_disable_irq(b);
|
|
if (intel_engine_has_waiter(engine)) {
|
|
b->timeout = wait_timeout();
|
|
__intel_breadcrumbs_enable_irq(b);
|
|
if (READ_ONCE(b->irq_posted))
|
|
wake_up_process(b->first_wait->tsk);
|
|
} else {
|
|
/* sanitize the IMR and unmask any auxiliary interrupts */
|
|
irq_disable(engine);
|
|
}
|
|
|
|
spin_unlock_irq(&b->lock);
|
|
}
|
|
|
|
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
|
|
{
|
|
struct intel_breadcrumbs *b = &engine->breadcrumbs;
|
|
|
|
if (!IS_ERR_OR_NULL(b->signaler))
|
|
kthread_stop(b->signaler);
|
|
|
|
cancel_fake_irq(engine);
|
|
}
|
|
|
|
unsigned int intel_kick_waiters(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
unsigned int mask = 0;
|
|
|
|
/* To avoid the task_struct disappearing beneath us as we wake up
|
|
* the process, we must first inspect the task_struct->state under the
|
|
* RCU lock, i.e. as we call wake_up_process() we must be holding the
|
|
* rcu_read_lock().
|
|
*/
|
|
for_each_engine(engine, i915, id)
|
|
if (unlikely(intel_engine_wakeup(engine)))
|
|
mask |= intel_engine_flag(engine);
|
|
|
|
return mask;
|
|
}
|
|
|
|
unsigned int intel_kick_signalers(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
unsigned int mask = 0;
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
if (unlikely(READ_ONCE(engine->breadcrumbs.first_signal))) {
|
|
wake_up_process(engine->breadcrumbs.signaler);
|
|
mask |= intel_engine_flag(engine);
|
|
}
|
|
}
|
|
|
|
return mask;
|
|
}
|